Performance evolution of 4-b bit MAC unit using hybrid GDI and transmission gate based adder and multiplier circuits in 180 and 90 nm technology

This paper presents the high-speed adder circuit design based on 18 transistor (18T) full swing gate diffusion input based logic gates and transmission based techniques to compute the sum and carry bits, respectively. The proposed adder logic operates at 1.8 and 1.2 V supply voltage. The 180 and 90 ...

Full description

Saved in:
Bibliographic Details
Published in:Microprocessors and microsystems 2018-06, Vol.59, p.15-28
Main Authors: Kandasamy, Nehru, Ahmad, Firdous, Reddy, Shashikanth, M, Ramesh Babu, Telagam, Nagarjuna, Utlapalli, Somanaidu
Format: Article
Language:English
Subjects:
Adding circuits
Circuit design
Circuits
Computer simulation
Delay
Diffusion
Evolution
Gates (circuits)
High speed
Logic circuits
Monte Carlo simulation
Parameters
Power reliability
Software
Transistors
Transmission gates
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:This paper presents the high-speed adder circuit design based on 18 transistor (18T) full swing gate diffusion input based logic gates and transmission based techniques to compute the sum and carry bits, respectively. The proposed adder logic operates at 1.8 and 1.2 V supply voltage. The 180 and 90 nm technology are used for the proposed architectures. The proposed design consists of less power delay products and reduces 28.57% as compared to conventional 16 transistor based adder cells. The proposed adder circuit increases the transistor count by a factor of 2. The performance of the proposed 1-bit adder circuit is testified to design 4-bit ripple carry, carry save and carry select adder circuits, with reduced circuit parameters in terms of power, delay and power delay products. In addition, the performance of the proposed adder circuit are checked to design Barun and Baugh Wooley multipliers. Finally, the low power and high-speed MAC unit is designed with the proposed adder, multiplier and register circuits. The proposed MAC unit achieves significant improvements in power-delay product as compared to conventional designs. The proposed adder, multiplier and MAC unit operation is performed wih the number of samples using Monte Carlo simulation tool. The performance evolution of the circuit parameters including power, delay and power-delay products are verified using the Cadence software Virtuoso software.
ISSN:0141-9331
DOI:10.1016/j.micpro.2018.03.003