PEAF: A Power-Efficient Architecture for SRAM-Based FPGAs Using Reconfigurable Hard Logic Design in Dark Silicon Era

Significant increase of static power in nano-CMOS era and, subsequently, the end of Dennard scaling has put a Power Wall to further integration of CMOS technology in Field-Programmable Gate Arrays (FPGAs). An efficient solution to cope with this obstacle is power gating inactive fractions of a singl...

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Bibliographic Details
Published in:IEEE transactions on computers 2017-06, Vol.66 (6), p.982-995
Main Authors: Ebrahimi, Zahra, Khaleghi, Behnam, Asadi, Hossein
Format: Article
Language:English
Subjects:
CMOS
dark silicon
Field programmable gate arrays
Gate arrays
hard logic
Logic design
Logic gates
Lookup tables
Mapping
Power efficiency
Reconfiguration
Routing
Silicon
SRAM
static power
Static random access memory
Table lookup
Transistors
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Summary:Significant increase of static power in nano-CMOS era and, subsequently, the end of Dennard scaling has put a Power Wall to further integration of CMOS technology in Field-Programmable Gate Arrays (FPGAs). An efficient solution to cope with this obstacle is power gating inactive fractions of a single die, resulting in Dark Silicon. Previous studies employing power gating on SRAM-based FPGAs have primarily focused on using large-input Look-up Tables (LUTs). The architectures proposed in such studies inherently suffer from poor logic utilization which limits the benefits of power gating techniques. This paper proposes a Power-Efficient Architecture for FPGAs (PEAF) based on combination of Reconfigurable Hard Logics (RHLs) and a small-input LUT. In the proposed architecture, we selectively turn off unused RHLs and/or LUTs within each logic block by employing a reconfigurable controller. By mapping a majority of logic functions to simple-design RHLs, PEAF is able to significantly improve power efficiency without deteriorating the performance. Experimental results over a comprehensive set of benchmarks (MCNC, IWLS'05, and VTR) demonstrate that compared with baseline four-LUT architecture, PEAF reduces the total static power and Power-Delay-Product (PDP), on average, by 24.5 and 21.7 percent, respectively. This is while the overall system performance is also improved by 1.8 percent. PEAF increases total area by 18.9 percent, however, it still occupies 22.1 percent less area footprint than the six-LUT architecture with 31.5 percent improvement in PDP.
ISSN:0018-9340
1557-9956
DOI:10.1109/TC.2016.2636141