An Accurate and Noise-Resilient Spread-Spectrum Clock Tracking Aid for Digitally-Controlled Clock and Data Recovery Loops

This paper presents a novel spread-spectrum clock (SSC) tracking aid for digitally-controlled clock and data recovery (CDR) loops. The proposed tracking aid accurately recovers the time instants when the slope of the incoming data frequency ramp changes its polarity, so that the CDR can preemptively...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2019-03, Vol.66 (3), p.1245-1257
Main Authors: Ryu, Sigang, Son, Seuk, Kim, Jaeha
Format: Article
Language:English
Subjects:
Clocks
Control theory
Data recovery
Data transmission
Digital clock and data recovery (DCDR)
digital loop filter (DLF)
Error analysis
Feedback loops
Frequency control
Frequency modulation
Negative feedback
Noise
Noise levels
Phase locked loops
Phase locked systems
Polarity
spread-spectrum clocking (SSC)
Time-frequency analysis
Timing
Tracking control
Tracking loops
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:This paper presents a novel spread-spectrum clock (SSC) tracking aid for digitally-controlled clock and data recovery (CDR) loops. The proposed tracking aid accurately recovers the time instants when the slope of the incoming data frequency ramp changes its polarity, so that the CDR can preemptively compensate the timing errors that can otherwise be incurred when relying on feedback controls only. Compared with the existing SSC tracking aids, the proposed tracking aid's integration-based mean-tracking loop, comprising an integrator and subsequent negative feedback loop, achieves the superior noise resilience and SSC timing accuracy. The analysis shows that the error in recovering the SSC deflection timing can be as low as 0.01% of the SSC modulation period in case of tracking a triangular SSC profile and the error does not exceed 1.5% even when the SSC profile noise is increased to the signal-to-noise-plusdistortion ratio of 20 dB. The behavioral simulation of a digitallycontrolled phase-locked loop (PLL)-based CDR employing the proposed SSC tracking aid demonstrates a 0.711-TiI timing margin with a BER of 10 -12 , which is a 1.57× improvement in comparison with a PLL-based second-order CDR, when tracking a 6-Gb/s data stream modulated with a 30-kHz, 50000-ppm extended triangular-shaped SSC profile.
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2018.2879614