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Mixed-Signal Overclocked I/O Buffers Model Abstraction for Signal Integrity Assessment

This paper addresses the development of a behavioral modeling abstraction methodology that reduces the model order complexity of the transistor level physical model describing the input-output (I/O) buffers that interface the digital (i.e., discrete) and the analog world in the high-speed digital co...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2019-03, Vol.27 (3), p.691-699
Main Authors: Dghais, Wael, Souilem, Malek, Alam, Muhammad
Format: Article
Language:English
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Summary:This paper addresses the development of a behavioral modeling abstraction methodology that reduces the model order complexity of the transistor level physical model describing the input-output (I/O) buffers that interface the digital (i.e., discrete) and the analog world in the high-speed digital communication I/O links. In fact, the proposed high-level hybrid automaton behavioral model (HABM) is analyzed as a mixed-signal modeling approach that combines both discrete and continuous abstractions. The modeling framework investigates the quantization of the on-off nonreturn-to-zero input signal to analyze the mixed signal behavior of the predriver and the analog dynamics of the I/O buffer's last stage for easing the model's extraction and running complexities while accurately predicting the I/O buffer's nonlinear switching behavior under normal and overclocking conditions. The time decomposition of the input and state variables enables the approximation of the predriver's nonlinear dynamic by means of digitally controlled linear dynamic filters. The filter's outputs are multiplexed and integrated with the continuous-time nonlinear dynamic model of driver's last stage output admittances. The implemented mixed-signal HABM presents more accurate transient simulation results than the I/O buffer information specification algorithm when assessing the signal integrity performance while alleviating the computational cost under overclocking operation.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2018.2885407