Custard: ASIC Workload-Aware Reliable Design for Multicore IoT Processors

• Published in: IEEE transactions on very large scale integration (VLSI) systems 2019-03, Vol.27 (3), p.700-710
• Main Authors: Lerner, Scott, Yilmaz, Isikcan, Taskin, Baris
• Format: Article
• Language: English
• Subjects: Circuit design; Circuit reliability; Component reliability; Computer simulation; Custard; Degradation; Form factors; Integrated circuits; Internet of Things; Internet of Things (IoT); lifetime; Logic; Microprocessors; multicore; Multicore processing; Negative bias temperature instability; Processors; Program processors; Reliability; Switches; Switching; Thermal simulation; Thermal simulators; Thermal variables control; Workload; workload aware; Workloads
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2018.2878664

In the typical application-specified integrated circuit (ASIC) design flow, reliability-driven performance loss is computed, in part, with switching activity files. However, for ASIC designs of multicore processors, the typical switching activity files lack multithreaded software workload information. An accurate switching activity for a multicore design can be generated using a logic simulator. However, the logic simulator process suffers from long runtimes when dealing with real workloads. This paper analyzes the effects of scaling multithreaded workloads and proposes Custard, a hardware methodology for lifetime improvement of multicore processors by obtaining multithreaded switching activity signatures in a short period of time using a performance simulator (gem5), logic simulator (VCS), and thermal simulator (HotSpot). Custard is particularly important for multicore, Internet of Things processors as the runtime feedback-based reliability mechanisms used on current multicore processors incur area and power overhead that could be prohibitive for smaller form factors and power budgets. Experiments are performed with Custard using real workloads on an OpenSPARC T1 design with two, four, and eight cores that are fully synthesized and routed. The default-sized T1 core is improved to have a reliability increase of 4.1\times , with 0.08% and 1.57% increase on average in cell area and switching power, respectively.