Methods to improve performance of instruction prefetching through balanced improvement of two primary performance factors

• Published in: Journal of systems architecture 1998-06, Vol.44 (9), p.755-772
• Main Authors: Park, Gi-Ho, Kwon, Oh-Young, Han, Tack-Don, Kim, Shin-Dug, Yang, Sung-Bong
• Format: Article
• Language: English
• Subjects: Applied sciences; Cache; Cache performance model with prefetching; Computer memory; Computer science; control theory; systems; Computer systems performance. Reliability; Exact sciences and technology; Hierarchies; Instruction cache; Instruction prefetching; Memory and file management (including protection and security); Memory organisation. Data processing; Performance analysis; Simulation; Software; Software engineering; Studies; Trace-driven simulation
• ISSN: 1383-7621; 1873-6165
• DOI: 10.1016/S1383-7621(97)00021-0

The performance of conventional instruction prefetching mechanisms (IPMs) is analyzed in this paper based on two performance factors, i.e., the cache miss ratio and the average access time for successfully prefetched blocks. Although significant performance improvement (PI) can be obtained by improving these two factors, most conventional prefetching mechanisms improve only one factor out of these two factors. Fetching multiple blocks for a prefetch request and prefetching the sequentially next block together with the block that causes a cache miss in lookahead prefetching (LP) are proposed to improve both these factors. A new method to initiate a prefetch request earlier with no degradation of the prefetch accuracy is also presented for a memory system that is constructed as an interleaved memory. Performance evaluation is carried out through trace-driven simulation and the proposed prefetch scheme reduces 45–63% of the memory access delay time (MADT) for the cache system that does not perform any prefetching.