Dependable design technique for system-on-chip

A technique for highly reliable digital design for two FPGAs under a processor control is presented. Two FPGAs are used in a duplex configuration system design, but better dependability parameters are obtained by the combination of totally self-checking blocks based on a parity predictor. Each FPGA...

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Bibliographic Details
Published in:Journal of systems architecture 2008-03, Vol.54 (3), p.452-464
Main Authors: Kubalík, Pavel, Kubátová, Hana
Format: Article
Language:English
Subjects:
Array processors
Control systems
Dependability calculations
Dependability model
Fault security
Field programmable gate arrays
FPGA
On-line testing
Reconfiguration
Reliable digital design
Self-testing
Single even upset
Studies
Systems design
Totally self-checking
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Summary:A technique for highly reliable digital design for two FPGAs under a processor control is presented. Two FPGAs are used in a duplex configuration system design, but better dependability parameters are obtained by the combination of totally self-checking blocks based on a parity predictor. Each FPGA can be reconfigured when a SEU fault is detected. This reconfiguration is controlled by a control unit implemented in a processor. Combinational circuit benchmarks have been considered in all our experiments and computations. All our experimental results are obtained from a XILINX FPGA implementation using EDA tools. The dependability model and dependability calculations are presented to document the improved reliability parameters.
ISSN:1383-7621
1873-6165
DOI:10.1016/j.sysarc.2007.09.003