Optimization Design on Active Guard Ring to Improve Latch-Up Immunity of CMOS Integrated Circuits

• Published in: IEEE transactions on electron devices 2019-04, Vol.66 (4), p.1648-1655
• Main Authors: Chen, Chun-Cheng, Ker, Ming-Dou
• Format: Article
• Language: English
• Subjects: Active guard ring; Circuit design; CMOS; Design optimization; electrostatic discharge (ESD) protection; Electrostatic discharges; guard ring; Immune system; Immunity; Integrated circuits; Latch-up; Layout; Logic gates; MOS devices; MOSFETs; Optimization; Robustness (mathematics); silicon-controlled rectifier (SCR); Static electricity; Substrates
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2019.2898317

A new optimization design of an active guard ring has been proposed to improve latch-up immunity of CMOS integrated circuits and been successfully verified in a 0.18- \mu \text{m} 1.8-/3.3-V CMOS technology. Codesigned with the on-chip electrostatic discharge (ESD) protection devices (gate-ground nMOS and gate-VDD pMOS) equipped at the input-output (I/O) pad, the overshooting/undershooting trigger current during latch-up test can be conducted away through the turned-on channels of the ESD protection MOSFET's to the power rails ( {V}_{\textsf {DD}} or {V}_{\textsf {SS}} ). Therefore, the trigger current injecting from the I/O devices (that directly connected to the I/O pad) through the substrate to initiate the latch-up occurrence at the internal circuit blocks can be significantly reduced. Thus, the latch-up immunity of the whole chip can be effectively improved under the same placement distance between the I/O cells and the internal circuit blocks. The new proposed design is a cost-efficient solution to improve latch-up immunity and also to mention good ESD robustness of the I/O cells.