Analysis of Parasitic Effects in Filamentary-Switching Memristive Memories Using an Approximated Verilog-A Memristor Model

• Published in: IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2019-05, Vol.66 (5), p.1935-1947
• Main Authors: Lupo, Nicola, Perez, Eduardo, Wenger, Christian, Maloberti, Franco, Bonizzoni, Edoardo
• Format: Article
• Language: English
• Subjects: Approximation; Computation; Computational modeling; Computer simulation; Design standards; filamentary-switching memristors; Hafnium compounds; Hafnium oxide; Integrated circuit modeling; Mathematical models; Memory devices; Memristive memories; memristor model; Memristors; Numerical models; Numerical stability; Parasitics (electronics); Resistance; Standardization; Switches
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2018.2882993

The technology for oxide resistive memories offers nowadays a number of different implementations and solutions. As a consequence, many models have been presented so far, generally technology-specific, representing a problem for the memory design standardization. Moreover, the computational effort can be reduced using memristive models with lower complexity but that grant at the same time good speed and numerical stability. In this paper, the authors try to find a compromise between accuracy and computational costs, proposing a simulation procedure based on a linear approximation of the memristive device model. The description, formally derived from the traditional linear model, has been implemented in Verilog-A and, thanks to the analysis of practical design cases on a reference architecture, has been demonstrated to be useful in highlighting critical parasitic effects related to the interaction of the memristive cells with the memory circuit periphery. Thanks to the approximated method, a computer simulation time saving up to 40% is achieved when simulating a full cross-bar memory device. The model parameters have been extracted from experimental curves obtained from HfO 2 devices implemented in a 250-nm BiCMOS IHP technology.