A Fully Integrated −32-dB EVM Broadband 802.11abgn/ac PA With an External PA Driver in WLP 40-nm CMOS

• Published in: IEEE transactions on microwave theory and techniques 2019-05, Vol.67 (5), p.1870-1882
• Main Authors: Ahn, Hyunjin, Back, Seungjun, Nam, Ilku, An, Deokgi, Lee, Jaekyoung, Jeong, Minsu, Kim, Bo-Eun, Lee, Young-Taek, Kim, Hong-Teuk, Ho, Yo-Chuol, Lee, Ockgoo
• Format: Article
• Language: English
• Subjects: Bandwidth; Bandwidths; Broadband; Broadband communication; Capacitors; CMOS; CMOS technology; Impedance; Impedance matching; Local area networks; Performance degradation; Performance enhancement; power amplifier (PA); Power amplifiers; Power efficiency; reconfigurable; State of the art; Technology utilization; transformer; wafer-level package (WLP); Wireless LAN; wireless local area network (WLAN); Wireless networks
• ISSN: 0018-9480; 1557-9670
• DOI: 10.1109/TMTT.2019.2899332

Even though CMOS-based power amplifiers (PAs) provide reductions in size and cost for wireless local area network (WLAN) applications, their performances must be improved to match those of HBT-based PAs. In this paper, a design methodology for WLAN CMOS PAs is proposed to obtain broadband performances with a compact area using the wafer-level package technology. To achieve a highly linear output power with high efficiency across a 1-GHz bandwidth in a 5G-band PA, a reconfigurable interstage matching network and a broadband compact output transformer are proposed. For applications requiring a high linear transmission power, an integrated CMOS PA in a full transmitter chain must support the operation with external HBT-based PAs. A structure involving a main internal PA with an external PA driver is proposed to support the external PA mode with low-current consumption. The proposed structure does not require additional components or an output port and does not have the performance degradation of the main internal PA. The implemented 2.4G-band/5G-band CMOS PA using 40-nm CMOS technology has an average output power in the ranges of 19.1-19.2/18.6-18.8 dBm in the respective ranges of 2.4-2.5/4.9-5.9 GHz and concurrently complies with the −32-dB error vector magnitude (EVM) requirement. The power-added efficiencies (PAEs) for the 2.4G-band/5G-band CMOS PA with a −32-dB EVM is 12.9%/12.2% at 2.45/5.5 GHz. To the best of the authors' knowledge, the presented PA exhibits the state-of-the-art minimum variation with high PAE and an output power in the range of 4.9-5.9 GHz compared to the fully integrated WiFi CMOS PAs reported thus far.