Scaling of Output Load in Energy Efficient FIR Filter for Green Communication on Ultra-Scale FPGA

• Published in: Wireless personal communications 2019-06, Vol.106 (4), p.1813-1826
• Main Authors: Pandey, Bishwajeet, Pandey, Nisha, Kaur, Amanpreet, Akbar Hussain, D. M., Das, Bhagwan, Tomar, Geetam S.
• Format: Article
• Language: English
• Subjects: Capacitance; Communications Engineering; Computer Communication Networks; Digital signal processing; Energy efficiency; Energy management; Engineering; Field programmable gate arrays; Filter design (mathematics); FIR filters; Linear phase; Networks; Power consumption; Power efficiency; Power management; Reduction; Scaling; Signal,Image and Speech Processing
• ISSN: 0929-6212; 1572-834X
• DOI: 10.1007/s11277-018-5717-2

FIR Filter always remains in linear phase with the help of symmetric coefficient. This feature makes it ideal for phase-sensitive applications like data communications. Design of FIR filter with energy efficiency makes excellent sense to achieve energy efficiency in digital selected frequency module of communication. We are using scaling of output load from 5000 to 0 pF to show an effect of output load on both on-chip and off-chip power consumption of FIR filter design. 20 nm technology based FVA1156 package and Kintex-7 family ultra-scale FPGA is taken under reconsideration for implementation of our model. With the use of HSTL_II IO standards, there is 84.39 and 92.83% reduction in IOs power when we scale down capacitance from 5000 to 500 and 0 pF respectively. With the use of HSTL_I_18 IO standards, there is 72.48 and 80.13% reduction in total on-chip power when we scale down capacitance from 5000 to 500 and 0 pF respectively. Along with IOs power and total on-chip power, we have also analyzed Off-chip device power, junction temperature, thermal margin, and different dynamic power likes Signal power, logic power, and DSP power.