Energy efficient low‐power full‐adder by 65 nm CMOS technology in ALU

Summary The arrangement of energy efficient low‐power full adder has vital role in VLSI systems. In this paper Energy Efficient Low‐power 9T full‐adder is proposed. Its functioning basis of Power Delay Product (PDP), Delay, power and area is distinguished in accordance with that current 1 bit full‐a...

Full description

Saved in:
Bibliographic Details
Published in:Concurrency and computation 2019-06, Vol.31 (12), p.n/a
Main Authors: N, Suresh Kumar, K, Paramasivam
Format: Article
Language:English
Subjects:
Adding circuits
area
average power
CMOS
Delay
Integrated circuits
Logic circuits
power delay product (PDP)
Semiconductor devices
Transistors
Citations: Items that this one cites
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Summary The arrangement of energy efficient low‐power full adder has vital role in VLSI systems. In this paper Energy Efficient Low‐power 9T full‐adder is proposed. Its functioning basis of Power Delay Product (PDP), Delay, power and area is distinguished in accordance with that current 1 bit full‐adder simulated by utilizing various Complementary MOS logic designs. Output provides an average minimization of 99.28% in power usage, 67.87% in area, 99.89% in delay, and 99.99% in Power‐Delay Product (PDP) distinguished to the traditional 28 Transistors CMOS logic. The ALU design has been implemented using 9T full adder. These logic gates are analysis at 65 nm technology of CMOS by utilizing Schematic Editor Tool.
ISSN:1532-0626
1532-0634
DOI:10.1002/cpe.4741