RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer

A physical design methodology is presented to synchronize digital application specific integrated circuit (ASIC) designs by a resonant rotary clock network. One novelty of the proposed RotaSYN flow is that the ASIC products of RotaSYN can operate at previously unattainable (relatively) low-frequency...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2019-07, Vol.66 (7), p.2685-2698
Main Authors: Kuttappa, Ragh, Balaji, Adarsha, Pano, Vasil, Taskin, Baris, Mahmoodi, Hamid
Format: Article
Language:English
Subjects:
Algorithms
Application specific integrated circuits
Capacitance
Circuit design
Clocks
Computer simulation
Delays
Distribution management
EDA
Electronic design automation
Frequency conversion
Frequency dividers
Frequency ranges
Integrated circuits
low power
Oscillators
Performance measurement
Phase locked loops
resonant clock
Resonant frequencies
Resonant frequency
Synthesis
Traveling waves
VLSI
Wires
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:A physical design methodology is presented to synchronize digital application specific integrated circuit (ASIC) designs by a resonant rotary clock network. One novelty of the proposed RotaSYN flow is that the ASIC products of RotaSYN can operate at previously unattainable (relatively) low-frequency ranges of hundreds of megahertz. The dynamic resonant frequency divider is used to implement the low-frequency operation; and low in comparison to the norm of gigahertz-range of operation for resonant clocking reported in this paper. In SPICE -based simulations, the efficacy of the proposed flow and novel algorithms in RotaSYN is demonstrated using performance metrics of the wirelength, skew, and power on international symposium on physical design-10 clock benchmark circuits. In addition, RotaSYN is compared to three publicly available industrial designs that include the ARM Cortex M0 against equivalent clocks generated with a traditional phase locked loop (PLL) and distributed with an industrial clock tree synthesis tool flow. The RotaSYN methodology is implemented at three different target frequencies of 880 MHz, 500 MHz, and 220 MHz for the industrial designs. SPICE simulations show an average of 29% power savings for the industrial designs overall, solely thanks to 66% power savings on the clock generation and distribution networks, operating at a frequency of 880 MHz on comparison to the PLL-based design with a clock tree synthesized with an industrial EDA tool.
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2019.2896815