Highly stable, low power FinFET SRAM cells with exploiting dynamic back-gate biasing

In this paper, we propose two independent gate (IG) FinFET SRAM cells that use PMOS access transistors and back-gate (BG) biasing to achieve a high-stability performance. In the first cell, the back-gate of the access transistors is connected to the adjacent storage nodes, and the back-gate of the p...

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Bibliographic Details
Published in:Integration (Amsterdam) 2019-03, Vol.65, p.128-137
Main Authors: Bagheriye, Leila, Toofan, Siroos, Saeidi, Roghayeh, Moradi, Farshad
Format: Article
Language:English
Subjects:
Cells
Control stability
Dynamic back-gate design
FinFET
Independent gate (IG)
Low power
Noise
Photovoltaic cells
Semiconductor devices
Studies
Transistors
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Summary:In this paper, we propose two independent gate (IG) FinFET SRAM cells that use PMOS access transistors and back-gate (BG) biasing to achieve a high-stability performance. In the first cell, the back-gate of the access transistors is connected to the adjacent storage nodes, and the back-gate of the pull-down transistors is dynamically biased. Simulations indicate that the first proposed cell offers higher read static noise-margin (SNM), higher write-ability, least static/dynamic power, and a comparable read current compared to the previous IG-6TSRAMs. The second cell is a novel independently-controlled-gate FinFET SRAM cell, which provides a high read stability, the highest write-ability, low static power dissipation and high read current compared to the previously reported independently-controlled-gate FinFET SchmitTrigger based SRAM cells. This cell supportsbit-interleaving property at VDD = 0.4 V with high read/write yields.
ISSN:0167-9260
1872-7522
DOI:10.1016/j.vlsi.2018.11.011