A 14-bit column-parallel two-step SA ADC with digital calibration based on scaled references and redundancy for CMOS image sensors

• Published in: Analog integrated circuits and signal processing 2019-08, Vol.100 (2), p.295-309
• Main Authors: Li, Zhelu, Xie, Ning, Fan, Wei, Xi, Jianxiong, He, Lenian, Sun, Kexu
• Format: Article
• Language: English
• Subjects: Analog to digital conversion; Analog to digital converters; Calibration; Capacitors; Circuits and Systems; CMOS; Digital imaging; Electrical Engineering; Engineering; Figure of merit; Redundancy; Sensor arrays; Sensors; Signal,Image and Speech Processing; Switching; Weight
• ISSN: 0925-1030; 1573-1979
• DOI: 10.1007/s10470-018-1368-1

A 14-bit column-parallel two-step successive approximation (SA) analog-to-digital converter (ADC) with digital calibration based on scaled references and redundancy for CMOS image sensors is presented. A 7-bit area-efficient non-binary capacitor array whose total number is same as the 6-bit one is used to meet the dimension constraints imposed by the pixel pitch of 25 μm in the CMOS image sensor. In each conversion period, 14-bit resolution is realized by 16-times comparison which provides redundancy for calibration. Capacitor mismatch and scaled-reference error both deviate the weight of each bit from its designed value. An off-chip digital calibration method based on statistics is adopted to extract the fabricated weight of each bit in the SA ADC. A tri-level switching scheme is employed for the most 8 significant times comparison to reduce switching power of the capacitor array of the SA ADC. The proposed SA ADC is implemented by using 180 nm CIS process and measured at 1 MS/s. The area of the SA ADC is 1637 × 50 μm 2 . It consumes 78.47 μA under 3.3 V supply voltage. The INL is improved from + 21/− 21 to + 2.3/− 2.5 LSB, SFDR from 73.56 to 85.17 dB and ENOB from 9.57 to 11.15 bit after calibration in the presence of capacitor mismatch and scaled reference errors. The figure of merit of the ADC is 118 fJ/Conv.-step.