A 7-GHz Fast-Lock Two-Step Time-to-Digital Converter-Based All-Digital DLL

This paper presents a new fast-lock all-digital delay-locked loop (DLL) for next-generation memory devices such as DDR5 SDRAMs. The proposed DLL utilizes a new two-step time-to-digital converter (TDC)-based phase detecting and tracking scheme that results in a fast lock time of less than seven clock...

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Bibliographic Details
Published in:Circuits, systems, and signal processing systems, and signal processing, 2020-04, Vol.39 (4), p.1715-1734
Main Authors: Park, Dongjun, Kim, Jongsun
Format: Article
Language:English
Subjects:
Circuits and Systems
CMOS
Converters
Delay
Electrical Engineering
Electronics and Microelectronics
Engineering
Frequency ranges
Instrumentation
Memory devices
Signal,Image and Speech Processing
Vibration
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Summary:This paper presents a new fast-lock all-digital delay-locked loop (DLL) for next-generation memory devices such as DDR5 SDRAMs. The proposed DLL utilizes a new two-step time-to-digital converter (TDC)-based phase detecting and tracking scheme that results in a fast lock time of less than seven clock cycles. Unlike previous TDC-based DLLs, there is an advantage of having a fast lock time regardless of the long-replica clock buffer delay in the DRAM DLL. Implemented in a 65 nm CMOS process, the proposed digital DLL has a wide operating frequency range of 1.65–7.0 GHz and occupies an area of only 0.021 mm 2 . The DLL dissipates only 7.1 mW from a 1.0 V supply at 7 GHz, and the effective peak-to-peak (p–p) jitter of the output clock is about 4.55 ps at 7 GHz.
ISSN:0278-081X
1531-5878
DOI:10.1007/s00034-019-01230-x