A new step response modeling in CMOS operational amplifiers

Settling time is one of the most important parameters in opamps with feedback. In this article, the step response of the fully differential single stage folded cascade architecture amplifiers is analyzed to investigate the behavior of settling time and slew rate. An important characteristic of the p...

Full description

Saved in:
Bibliographic Details
Published in:Analog integrated circuits and signal processing 2019-10, Vol.101 (1), p.45-55
Main Authors: Gholamnataj, Hannane, Adarang, Habib, Mohseni, Seyed Saleh, Ghoreishi, Seyed Saleh
Format: Article
Language:English
Subjects:
Circuit design
Circuits and Systems
CMOS
Computer simulation
Electrical Engineering
Electronics
Engineering
Integrated circuits
Mathematical models
Operational amplifiers
Semiconductor devices
Settling
Settling behavior
Signal,Image and Speech Processing
Slew rate
Step response
Transistors
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Settling time is one of the most important parameters in opamps with feedback. In this article, the step response of the fully differential single stage folded cascade architecture amplifiers is analyzed to investigate the behavior of settling time and slew rate. An important characteristic of the proposed analytical model is that the behavior of the transistors is examined in detail after applying the step in the input, and it is shown that the settling time as well as slew rate would depend on the size of the input step. The resulting model can be beneficial for design and manual calculations in integrated circuits. Moreover, to examine the validity and precision of the resulting model, various simulations are performed, which show excellent matching between the proposed analytical model and the simulation results.
ISSN:0925-1030
1573-1979
DOI:10.1007/s10470-019-01485-z