Loading…
Split-Array, C-2C Switched-Capacitor Power Amplifiers
This paper presents a 13-b C-2C split-array (SA) multiphase switched-capacitor power amplifier (SAMP-SCPA) implemented in 65-nm CMOS. The SAMP-SCPA was designed for 16-b resolution to offer extra states for linearization/calibration using digital pre-distortion (DPD). Resolution limits for SA SCPAs...
Saved in:
Published in: | IEEE journal of solid-state circuits 2018-06, Vol.53 (6), p.1666-1677 |
---|---|
Main Authors: | , , , , |
Format: | Article |
Language: | English |
Subjects: | |
Citations: | Items that this one cites Items that cite this one |
Online Access: | Get full text |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
cited_by | cdi_FETCH-LOGICAL-c293t-ec9ad48a0d68015771add086af68b8338aed3c5031abc143c8d6c23626d406253 |
---|---|
cites | cdi_FETCH-LOGICAL-c293t-ec9ad48a0d68015771add086af68b8338aed3c5031abc143c8d6c23626d406253 |
container_end_page | 1677 |
container_issue | 6 |
container_start_page | 1666 |
container_title | IEEE journal of solid-state circuits |
container_volume | 53 |
creator | Bai, Zhidong Azam, Ali Johnson, Dallas Yuan, Wen Walling, Jeffrey S. |
description | This paper presents a 13-b C-2C split-array (SA) multiphase switched-capacitor power amplifier (SAMP-SCPA) implemented in 65-nm CMOS. The SAMP-SCPA was designed for 16-b resolution to offer extra states for linearization/calibration using digital pre-distortion (DPD). Resolution limits for SA SCPAs are presented. The SAMP-SCPA allows for the improvement of the SCPA resolution while minimizing the impact on the input power required driving it. A prototype SAMP-SCPA, occupying 0.85 mm \times 2 mm, delivers a peak output power of 24 dBm with a peak system efficiency (SE) of 40% at 1.8 GHz. When amplifying a long-term evolution (LTE) signal, the average output power and SE are 18.8 dBm and 21.6%, respectively, with an adjacent channel leakage ration (ACLR) < −30 dBc and error vector magnitude (EVM) of 2.65% rms. The increased resolution allows output power to be traded off for improved linearity and a low power mode demonstrates an EVM as low as 1% rms. |
doi_str_mv | 10.1109/JSSC.2018.2805872 |
format | article |
fullrecord | <record><control><sourceid>proquest_cross</sourceid><recordid>TN_cdi_proquest_journals_2298215954</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>8305507</ieee_id><sourcerecordid>2298215954</sourcerecordid><originalsourceid>FETCH-LOGICAL-c293t-ec9ad48a0d68015771add086af68b8338aed3c5031abc143c8d6c23626d406253</originalsourceid><addsrcrecordid>eNo9kE1Lw0AQhhdRsFZ_gHgJeHXrzG42mRxD8JOCQhS8LdvdDaa0Ju6mlP57U1o8DS_zvDPwMHaNMEOE4v61rquZAKSZIFCUixM2QaWIYy6_TtkExhUvBMA5u4hxOcY0JZwwVferduBlCGZ3l1RcVEm9bQf77R2vTG9sO3Qhee-2PiTlemSb1od4yc4as4r-6jin7PPx4aN65vO3p5eqnHMrCjlwbwvjUjLgMgJUeY7GOaDMNBktSEoy3kmrQKJZWEylJZdZITORuRQyoeSU3R7u9qH73fg46GW3CT_jSy1EQQJVodKRwgNlQxdj8I3uQ7s2YacR9N6O3tvRezv6aGfs3Bw6rff-nycJSkEu_wBof14-</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>2298215954</pqid></control><display><type>article</type><title>Split-Array, C-2C Switched-Capacitor Power Amplifiers</title><source>IEEE Xplore (Online service)</source><creator>Bai, Zhidong ; Azam, Ali ; Johnson, Dallas ; Yuan, Wen ; Walling, Jeffrey S.</creator><creatorcontrib>Bai, Zhidong ; Azam, Ali ; Johnson, Dallas ; Yuan, Wen ; Walling, Jeffrey S.</creatorcontrib><description>This paper presents a 13-b C-2C split-array (SA) multiphase switched-capacitor power amplifier (SAMP-SCPA) implemented in 65-nm CMOS. The SAMP-SCPA was designed for 16-b resolution to offer extra states for linearization/calibration using digital pre-distortion (DPD). Resolution limits for SA SCPAs are presented. The SAMP-SCPA allows for the improvement of the SCPA resolution while minimizing the impact on the input power required driving it. A prototype SAMP-SCPA, occupying 0.85 mm <inline-formula> <tex-math notation="LaTeX">\times </tex-math></inline-formula> 2 mm, delivers a peak output power of 24 dBm with a peak system efficiency (SE) of 40% at 1.8 GHz. When amplifying a long-term evolution (LTE) signal, the average output power and SE are 18.8 dBm and 21.6%, respectively, with an adjacent channel leakage ration (ACLR) < −30 dBc and error vector magnitude (EVM) of 2.65% rms. The increased resolution allows output power to be traded off for improved linearity and a low power mode demonstrates an EVM as low as 1% rms.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2018.2805872</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Arrays ; C-2C array ; Capacitance ; Capacitors ; class-D power amplifier (PA) ; Clocks ; CMOS ; digital PA ; Linearity ; multiphase switched-capacitor power amplifier (SCPA) ; Power amplifiers ; Power generation ; Radio frequency ; radio frequency digital-to-analog converter (RF DAC) ; Switches</subject><ispartof>IEEE journal of solid-state circuits, 2018-06, Vol.53 (6), p.1666-1677</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2018</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c293t-ec9ad48a0d68015771add086af68b8338aed3c5031abc143c8d6c23626d406253</citedby><cites>FETCH-LOGICAL-c293t-ec9ad48a0d68015771add086af68b8338aed3c5031abc143c8d6c23626d406253</cites><orcidid>0000-0003-0863-4182</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/8305507$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,27924,27925,54796</link.rule.ids></links><search><creatorcontrib>Bai, Zhidong</creatorcontrib><creatorcontrib>Azam, Ali</creatorcontrib><creatorcontrib>Johnson, Dallas</creatorcontrib><creatorcontrib>Yuan, Wen</creatorcontrib><creatorcontrib>Walling, Jeffrey S.</creatorcontrib><title>Split-Array, C-2C Switched-Capacitor Power Amplifiers</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>This paper presents a 13-b C-2C split-array (SA) multiphase switched-capacitor power amplifier (SAMP-SCPA) implemented in 65-nm CMOS. The SAMP-SCPA was designed for 16-b resolution to offer extra states for linearization/calibration using digital pre-distortion (DPD). Resolution limits for SA SCPAs are presented. The SAMP-SCPA allows for the improvement of the SCPA resolution while minimizing the impact on the input power required driving it. A prototype SAMP-SCPA, occupying 0.85 mm <inline-formula> <tex-math notation="LaTeX">\times </tex-math></inline-formula> 2 mm, delivers a peak output power of 24 dBm with a peak system efficiency (SE) of 40% at 1.8 GHz. When amplifying a long-term evolution (LTE) signal, the average output power and SE are 18.8 dBm and 21.6%, respectively, with an adjacent channel leakage ration (ACLR) < −30 dBc and error vector magnitude (EVM) of 2.65% rms. The increased resolution allows output power to be traded off for improved linearity and a low power mode demonstrates an EVM as low as 1% rms.</description><subject>Arrays</subject><subject>C-2C array</subject><subject>Capacitance</subject><subject>Capacitors</subject><subject>class-D power amplifier (PA)</subject><subject>Clocks</subject><subject>CMOS</subject><subject>digital PA</subject><subject>Linearity</subject><subject>multiphase switched-capacitor power amplifier (SCPA)</subject><subject>Power amplifiers</subject><subject>Power generation</subject><subject>Radio frequency</subject><subject>radio frequency digital-to-analog converter (RF DAC)</subject><subject>Switches</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2018</creationdate><recordtype>article</recordtype><recordid>eNo9kE1Lw0AQhhdRsFZ_gHgJeHXrzG42mRxD8JOCQhS8LdvdDaa0Ju6mlP57U1o8DS_zvDPwMHaNMEOE4v61rquZAKSZIFCUixM2QaWIYy6_TtkExhUvBMA5u4hxOcY0JZwwVferduBlCGZ3l1RcVEm9bQf77R2vTG9sO3Qhee-2PiTlemSb1od4yc4as4r-6jin7PPx4aN65vO3p5eqnHMrCjlwbwvjUjLgMgJUeY7GOaDMNBktSEoy3kmrQKJZWEylJZdZITORuRQyoeSU3R7u9qH73fg46GW3CT_jSy1EQQJVodKRwgNlQxdj8I3uQ7s2YacR9N6O3tvRezv6aGfs3Bw6rff-nycJSkEu_wBof14-</recordid><startdate>20180601</startdate><enddate>20180601</enddate><creator>Bai, Zhidong</creator><creator>Azam, Ali</creator><creator>Johnson, Dallas</creator><creator>Yuan, Wen</creator><creator>Walling, Jeffrey S.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0003-0863-4182</orcidid></search><sort><creationdate>20180601</creationdate><title>Split-Array, C-2C Switched-Capacitor Power Amplifiers</title><author>Bai, Zhidong ; Azam, Ali ; Johnson, Dallas ; Yuan, Wen ; Walling, Jeffrey S.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c293t-ec9ad48a0d68015771add086af68b8338aed3c5031abc143c8d6c23626d406253</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2018</creationdate><topic>Arrays</topic><topic>C-2C array</topic><topic>Capacitance</topic><topic>Capacitors</topic><topic>class-D power amplifier (PA)</topic><topic>Clocks</topic><topic>CMOS</topic><topic>digital PA</topic><topic>Linearity</topic><topic>multiphase switched-capacitor power amplifier (SCPA)</topic><topic>Power amplifiers</topic><topic>Power generation</topic><topic>Radio frequency</topic><topic>radio frequency digital-to-analog converter (RF DAC)</topic><topic>Switches</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Bai, Zhidong</creatorcontrib><creatorcontrib>Azam, Ali</creatorcontrib><creatorcontrib>Johnson, Dallas</creatorcontrib><creatorcontrib>Yuan, Wen</creatorcontrib><creatorcontrib>Walling, Jeffrey S.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Xplore</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Bai, Zhidong</au><au>Azam, Ali</au><au>Johnson, Dallas</au><au>Yuan, Wen</au><au>Walling, Jeffrey S.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Split-Array, C-2C Switched-Capacitor Power Amplifiers</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>2018-06-01</date><risdate>2018</risdate><volume>53</volume><issue>6</issue><spage>1666</spage><epage>1677</epage><pages>1666-1677</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>This paper presents a 13-b C-2C split-array (SA) multiphase switched-capacitor power amplifier (SAMP-SCPA) implemented in 65-nm CMOS. The SAMP-SCPA was designed for 16-b resolution to offer extra states for linearization/calibration using digital pre-distortion (DPD). Resolution limits for SA SCPAs are presented. The SAMP-SCPA allows for the improvement of the SCPA resolution while minimizing the impact on the input power required driving it. A prototype SAMP-SCPA, occupying 0.85 mm <inline-formula> <tex-math notation="LaTeX">\times </tex-math></inline-formula> 2 mm, delivers a peak output power of 24 dBm with a peak system efficiency (SE) of 40% at 1.8 GHz. When amplifying a long-term evolution (LTE) signal, the average output power and SE are 18.8 dBm and 21.6%, respectively, with an adjacent channel leakage ration (ACLR) < −30 dBc and error vector magnitude (EVM) of 2.65% rms. The increased resolution allows output power to be traded off for improved linearity and a low power mode demonstrates an EVM as low as 1% rms.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/JSSC.2018.2805872</doi><tpages>12</tpages><orcidid>https://orcid.org/0000-0003-0863-4182</orcidid><oa>free_for_read</oa></addata></record> |
fulltext | fulltext |
identifier | ISSN: 0018-9200 |
ispartof | IEEE journal of solid-state circuits, 2018-06, Vol.53 (6), p.1666-1677 |
issn | 0018-9200 1558-173X |
language | eng |
recordid | cdi_proquest_journals_2298215954 |
source | IEEE Xplore (Online service) |
subjects | Arrays C-2C array Capacitance Capacitors class-D power amplifier (PA) Clocks CMOS digital PA Linearity multiphase switched-capacitor power amplifier (SCPA) Power amplifiers Power generation Radio frequency radio frequency digital-to-analog converter (RF DAC) Switches |
title | Split-Array, C-2C Switched-Capacitor Power Amplifiers |
url | http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-27T00%3A13%3A17IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Split-Array,%20C-2C%20Switched-Capacitor%20Power%20Amplifiers&rft.jtitle=IEEE%20journal%20of%20solid-state%20circuits&rft.au=Bai,%20Zhidong&rft.date=2018-06-01&rft.volume=53&rft.issue=6&rft.spage=1666&rft.epage=1677&rft.pages=1666-1677&rft.issn=0018-9200&rft.eissn=1558-173X&rft.coden=IJSCBC&rft_id=info:doi/10.1109/JSSC.2018.2805872&rft_dat=%3Cproquest_cross%3E2298215954%3C/proquest_cross%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-c293t-ec9ad48a0d68015771add086af68b8338aed3c5031abc143c8d6c23626d406253%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_pqid=2298215954&rft_id=info:pmid/&rft_ieee_id=8305507&rfr_iscdi=true |