Wideband Dual-Injection Path Self-Interference Cancellation Architecture for Full-Duplex Transceivers

• Published in: IEEE journal of solid-state circuits 2018-06, Vol.53 (6), p.1563-1576
• Main Authors: Zhang, Tong, Su, Chenxin, Najafi, Ali, Rudell, Jacques Christophe
• Format: Article
• Language: English
• Subjects: Adaptive filters; Adaptive finite-impulse response (FIR) filters; Architecture; Attenuation; Bandwidths; Broadband; Cancellation; Cancellers; Circuits; Circulators; CMOS integrated circuits; delay lines; fifth generation (5G) mobile communication; Finite impulse response filters; FIR filters; Impulse response; Integrated circuit modeling; Interference; interference cancellation; Linearity; Noise; Noise levels; Power amplifiers; Power consumption; Radio frequency; radio spectrum management; Transceivers; Wideband
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2018.2805874

A transceiver front end including a dual-injection path self-interference (SI) cancellation architecture is proposed for use in wideband full-duplex networks. The SI cancellation circuitry is implemented using: 1) one feedforward cancellation path containing a five-tap analog adaptive finite-impulse response (FIR) filter between the transmitter (TX) output and the receiver (RX) input; 2) a second baseband (BB) cancellation path containing a 14-tap low-frequency FIR filter with a point of injection at the RX BB output; 3) a phase noise cancellation method that suppresses the reciprocal mixing products associated with the downconversion in the BB cancellation path for the TX SI signal; and 4) an integrated noise cancelling power amplifier (PA). A prototype of 40-nm TSMC device was fabricated, which demonstrates more than 50-dB SI cancellation over 42-MHz bandwidth and a 10-dB attenuation of TX SI phase noise in the RX signal path. The two cancelling filters dissipate 11.5 mW, with a measured P_{\mathrm {-1\,dB}} and IIP 3 of 27/26.5 and 36/34.5 dBm, respectively. The RX noise figure is degraded by less than 1.55 dB, when both cancellers are enabled. The PA has a measured output of P_{\mathrm {-1\,dB}}/P_{\mathrm {sat}} of 25.1/26.5 dBm, respectively. The total chip die area is 3.5 mm 2 with an overall transceiver power consumption of 49 mW, excluding the integrated PA.