Compact FPGA architectures for the two-band fast discrete Hartley transform

The discrete Hartley transform is a real valued transform similar to the complex Fourier transform that finds numerous applications in a variety of fields including pattern recognition and signal and image processing. In this paper, we propose and study two compact and versatile hardware architectur...

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Bibliographic Details
Published in:Microprocessors and microsystems 2018-09, Vol.61, p.117-125
Main Authors: Pyrgas, Lampros, Kitsos, Paris, Skodras, Athanassios
Format: Article
Language:English
Subjects:
Adding circuits
Architecture
Digital signal processing
Digital signal processors
Embedded systems
Field programmable gate arrays
Fourier transforms
FPGA architecture
Hardware
Image processing
Modular structures
Multiplexers
Multipliers
Object recognition
Pattern recognition
Signal processing
Subtraction
Two-band fast discrete hartley transform
Ubiquitous computing
VHDL
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Summary:The discrete Hartley transform is a real valued transform similar to the complex Fourier transform that finds numerous applications in a variety of fields including pattern recognition and signal and image processing. In this paper, we propose and study two compact and versatile hardware architectures for the computation of the 8-point, 16-point and 32-point Two-Band Fast Discrete Hartley Transform. These highly modular architectures have a symmetric and regular structure consisting of two blocks, a multiplication block and an addition/subtraction block. The first architecture utilizes 8 multipliers and 16 adders/subtractors, achieving a maximum clock frequency of 95 MHz. The second architecture utilizes only 4 multipliers and 8 adders/subtractors, achieving a maximum clock frequency of 100 MHz; however it requires additional multiplexers and more clock cycles (from 1 to 58 clock cycles depends on the points) for the computation. As a result, the proposed hardware architectures constitute an efficient choice for area-restricted applications such as embedded or pervasive computing systems.
ISSN:0141-9331
1872-9436
DOI:10.1016/j.micpro.2018.06.002