An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators

This article presents a cascaded architecture of a frequency synthesizer to generate ultra-low-jitter output signals in a millimeter-wave (mmW) frequency band from 28 to 31 GHz. The mmW-band injection-locked frequency multiplier (ILFM) placed at the second stage has a wide bandwidth so that the perf...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2019-12, Vol.54 (12), p.3466-3477
Main Authors: Kim, Juyeop, Lim, Younghyun, Yoon, Heein, Lee, Yongsun, Park, Hangi, Cho, Yoonseo, Seong, Taeho, Choi, Jaehyouk
Format: Article
Language:English
Subjects:
Bandwidths
Cascaded
CMOS
Comparators
digital phase-locked loop (DPLL)
Electric potential
Frequencies
Frequency multipliers
frequency synthesizer
Frequency synthesizers
integrated phase noise (IPN)
Jitter
Millimeter wave communication
Millimeter waves
millimeter-waveband (mmW-band)
Phase locked loops
Phase locked systems
Phase noise
Power consumption
subsampling
Synthesis
Synthesizers
Vibration
Voltage
Voltage-controlled oscillators
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Summary:This article presents a cascaded architecture of a frequency synthesizer to generate ultra-low-jitter output signals in a millimeter-wave (mmW) frequency band from 28 to 31 GHz. The mmW-band injection-locked frequency multiplier (ILFM) placed at the second stage has a wide bandwidth so that the performance of the jitter of this frequency synthesizer is determined by the GHz-band, digital subsampling phase-locked loop (SSPLL) at the first stage. To suppress the quantization noise of the digital SSPLL while using a small amount of power, the optimally spaced voltage comparators (OSVCs) are presented as a voltage quantizer. This article was designed and fabricated using 65-nm CMOS technology. In measurements, this prototype frequency synthesizer generated output signals in the range of 28-31 GHz, with an rms jitter of less than 80 fs and an integrated phase noise (IPN) of less than -40 dBc. The active silicon area was 0.32 mm 2 , and the total power consumption was 41.8 mW.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2019.2936765