A Fully Digital Semirotational Frequency Detection Algorithm for Bang-Bang CDRs

• Published in: IEEE transactions on very large scale integration (VLSI) systems 2019-12, Vol.27 (12), p.2944-2948
• Main Authors: Kwon, Soon-Won, Bae, Hyeon-Min
• Format: Article
• Language: English
• Subjects: Algorithms; Circuit design; Clocks; CMOS; Data recovery; Detectors; Frequency detector; Frequency variation; Integrated circuits; Phase detectors; referenceless clock and data recovery (CDR); serial links; Temperature effects; Transceivers; Tuning; Very large scale integration; Voltage controlled oscillators
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2019.2940438

This brief presents a new frequency acquisition method using a semirotational frequency detection (SRFD) algorithm for referenceless clock and data recovery (CDR) in a serial-link receiver. The proposed SRFD algorithm classifies the bang-bang phase detector (BBPD) outputs to estimate the current phase state and detects the frequency mismatch between the input data and the sampling clock. The voltage-controlled oscillator (VCO)-track path in a digital loop filter (DLF) enables online calibration of a drifted frequency of the VCO caused by temperature or voltage variation after a frequency acquisition. The proposed algorithm can be implemented as a digitally synthesized circuit, lowering design efforts for referenceless CDRs. A 10-Gb/s transceiver IC with the proposed algorithm, fabricated in a 65-nm CMOS process, demonstrates successful recovery of the input phase without any reference clock.