Design of CMOS low-dropout voltage regulator for power management integrated circuit in 0.18-µm technology

• Published in: AIP conference proceedings 2020-01, Vol.2203 (1)
• Main Authors: Murad, S. A. Z., Harun, A., Isa, M. N. M., Mohyar, S. N., Sapawi, R., Karim, J.
• Format: Article
• Language: English
• Subjects: Circuit design; CMOS; Current mirrors; Integrated circuits; Power consumption; Power management; Resistors; Semiconductor devices; Transistors; Voltage; Voltage regulators
• ISSN: 0094-243X; 1551-7616
• DOI: 10.1063/1.5142098

A low-dropout (LDO) voltage regulator is the main component used in the majority of portable electronic application since it is used as power management unit in those applications. In this paper, a LDO regulator for the power management integrated circuit in 0.18-µm CMOS technology using Cadence software is presented. The error amplifier of the proposed LDO employed seven transistors for current mirror. Meanwhile, the PMOS transistor is used as a pass element transistor to control the voltage variation. The resistors are used as a feedback network circuit while the capacitor is used to minimise the variation of output voltage. The simulation results show that the proposed design provides a 2.41 V constant output voltage for the supply voltage ranges of 2.55 V to 3.55 V. The dropout voltage of 140 mV is achieved with 1.48 mW power consumption. The line regulation is 1.0 mV/V and the load regulation is 0.41 mV/A, while the layout of the proposed regulator is 27 µm x 34 µm.