Low-Frequency Noise in Vertically Stacked Si n-Channel Nanosheet FETs

This manuscript presents a systematic low-frequency noise analysis of inversion-mode vertically stacked silicon n-channel nanosheet MOSFETs on bulk wafers. Flicker noise due to carrier number fluctuations is shown as the dominant noise source, which is in line with previous reported studies on gate-...

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Bibliographic Details
Published in:IEEE electron device letters 2020-03, Vol.41 (3), p.317-320
Main Authors: de Oliveira, Alberto V., Veloso, Anabela, Claeys, Cor, Horiguchi, Naoto, Simoen, Eddy
Format: Article
Language:English
Subjects:
Carrier number fluctuations
Flicker
flicker noise
Frequency analysis
Gallium arsenide
gate–all–around
input–referred voltage power spectral density
Logic gates
low–frequency–noise
MOSFET
MOSFETs
Nanosheets
Nanowires
n–channel
oxide trap density
Power spectral density
Scattering
Silicon
silicon device
Variation
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Summary:This manuscript presents a systematic low-frequency noise analysis of inversion-mode vertically stacked silicon n-channel nanosheet MOSFETs on bulk wafers. Flicker noise due to carrier number fluctuations is shown as the dominant noise source, which is in line with previous reported studies on gate-all-around (GAA) nanowire nMOSFETs. In addition, the benchmark points out that the vertical stacking approach does not deteriorate the oxide trap density, since its normalized input-referred voltage noise Power Spectral Density at flat-band is lower compared to the data on non-stacked horizontal nanowire nMOSFETs. Another finding is that the Coulomb scattering mechanism dominates the mobility.
ISSN:0741-3106
1558-0563
DOI:10.1109/LED.2020.2968093