Modeling of NBTS Effects in P-Channel Power VDMOSFETs

• Published in: IEEE transactions on device and materials reliability 2020-03, Vol.20 (1), p.204-213
• Main Authors: Dankovic, Danijel, Mitrovic, Nikola, Prijic, Zoran, Stojadinovic, Ninoslav D.
• Format: Magazinearticle
• Language: English
• Subjects: Bias; Circuits; Degradation; Integrated circuit modeling; Logic gates; Low level; Modeling; Modelling; NBTI; Negative bias temperature instability; recoverable; Stress; Thermal variables control; Threshold voltage; Transistors; VDMOS
• ISSN: 1530-4388; 1558-2574
• DOI: 10.1109/TDMR.2020.2974131

This paper studies negative bias temperature instability in commercial IRF9520 p-channel power VDMOSFETs under both static and pulsed bias stress conditions in order to model this effect. The pulsed voltage stressing caused generally lower shifts as compared to static stressing performed at the same temperature with equal stress voltage magnitude, as a consequence of partial recovery during the low level of pulsed gate voltage. It was shown that the quantitative differences between static and pulsed NBT stress depend on the duty cycle, and the differences become more significant as the duty cycle decreases. It was found that 25 μs off-time of the pulsed stress voltage could suffice to remove the major part of the recoverable component of the degradation created during the foregoing pulse on-time. An equivalent electrical circuit has been proposed and on the basis of these experimental results a modeling of threshold voltage shifts induced by pulsed negative bias temperature stress has been done.