Achieving Picosecond-Level Phase Stability in Timing Distribution Systems With Xilinx Ultrascale Transceivers

This article discusses the challenges posed on the field-programmable gate array (FPGA) transceivers in terms of phase-determinism requirements for timing distribution at the Large Hadron Collider (LHC) experiments. Having a fixed phase after startups is a major requirement, and the typical phase va...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on nuclear science 2020-03, Vol.67 (3), p.473-481
Main Authors: Mendes, Eduardo, Baron, Sophie, Soos, Csaba, Troska, Jan, Novellini, Paolo
Format: Article
Language:English
Subjects:
Clocks
Detectors
Determinism
Fast timing
Field programmable gate arrays
field-programmable gate arrays (FPGAs)
High speed
high-energy physics instrumentation
Large Hadron Collider
optical links
Phase stability
Phase variations
Timing
timing circuits
Transceivers
Transmitters
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:This article discusses the challenges posed on the field-programmable gate array (FPGA) transceivers in terms of phase-determinism requirements for timing distribution at the Large Hadron Collider (LHC) experiments. Having a fixed phase after startups is a major requirement, and the typical phase variations observed in the order of tens of picoseconds after startups while using the state-of-the-art design techniques are no longer sufficient. Each limitation observed in the transmitter and receiver paths of the high-speed transceivers embedded in the Xilinx Ultrascale FPGA family is further investigated and solutions are proposed. Tests in hardware using Xilinx FPGA evaluation boards are presented. In addition to a higher phase determinism, the techniques presented make it possible to fine-tune the skew of a link with a picosecond resolution, greatly simplifying clock-domain crossing inside the FPGAs and providing better short-term stability for the FPGA-recovered clock in a high-speed link.
ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.2020.2968112