Analytical Model for Low-Frequency Noise in Junctionless Nanowire Transistors

This article aims at proposing a compact analytical model for the low-frequency noise (LFN) of junctionless nanowire transistors (JNTs), operating at different bias conditions and temperatures. The model is validated through tridimensional numerical simulations, accounting for different trap configu...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2020-06, Vol.67 (6), p.2536-2543, Article 2536
Main Authors: Trevisoli, Renan, Pavanello, Marcelo Antonio, Capovilla, Carlos Eduardo, Barraud, Sylvain, Doria, Rodrigo Trevisoli
Format: Article
Language:English
Subjects:
Analytical model
Analytical models
Automotive parts
Computer simulation
Electric potential
Electron traps
interface traps
junctionless
LF noise
Logic gates
low-frequency noise (LFN)
Mathematical model
Mathematical models
Model accuracy
Nanowires
Numerical models
Semiconductor devices
Transistors
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Summary:This article aims at proposing a compact analytical model for the low-frequency noise (LFN) of junctionless nanowire transistors (JNTs), operating at different bias conditions and temperatures. The model is validated through tridimensional numerical simulations, accounting for different trap configurations, as well as devices with different channel lengths, nanowire widths, and doping concentrations. Experimental results of short-channel junctionless transistors have also been used to demonstrate the model's applicability and accuracy.
ISSN:0018-9383
1557-9646
1557-9646
DOI:10.1109/TED.2020.2986141