Comprehensive Analysis and Optimization of Reliable Viterbi Decoder Circuits Implemented in Modular VLSI Design Logic Styles

• Published in: Journal of electronic testing 2020-06, Vol.36 (3), p.343-363
• Main Authors: Varada, Sushanth, Katpally, Swapnil, Thiruveedhi, Subha Sri Lakshmi
• Format: Article
• Language: English
• Subjects: Algorithms; CAE) and Design; Circuit design; Circuit reliability; Circuits and Systems; CMOS; Computer simulation; Computer-Aided Engineering (CAD; Design; Dissipation factor; Electrical Engineering; Electronic devices; Engineering; Error correction & detection; Error detection; Extreme values; Integrated circuits; Iterative methods; Logic; Markov chains; Markov processes; Modular design; Optimization; Power consumption; Power management; Semiconductor devices; Speech recognition; Transistors; Viterbi algorithm detectors; Viterbi decoders; Viterbi decoding
• ISSN: 0923-8174; 1573-0727
• DOI: 10.1007/s10836-020-05882-5

The Viterbi Algorithm is a recursive optimal solution for estimating the most likely state sequence of discrete-time finite-state Markov process and Hidden Markov Models (HMM) observed in memoryless noise. The Viterbi algorithm is extensively used for decoding convolutional codes, in the constraint length k that encompasses its use in digital communications specifically in satellite and cellular communications. Storage devices to speed up access, speech synthesis and recognition technologies use the Viterbi algorithm or its variants. In this paper low-power, high-speed and reduced transistor count Viterbi decoding circuits with enhanced error detection capabilities are designed and implemented with signature-based error detection schemes in three design logic styles primarily Conventional CMOS, Hybrid logic and GDI. The significance of the work is the upshot of realizing low latency and low power dissipation with high reliability in the iterative process of finding the least path metric by superseding the subtractor in CSA & PCSA circuits with an optimized comparator. When evaluated against the Traditional/Benchmark CSA & PCSA circuits, the Conventional CMOS design approach attains low power consumption and high accuracy with a reduction in average power dissipation by 4.69% and 3.83% and an improvement in delay performance by 7.89% and 3.79% respectively, with a tradeoff for high area utilization. Whereas, the GDI design approach results in an extreme reduction of transistor count by 71.52% and 74.94% with a weaker logic swing for CSA & PCSA units respectively, complimented by an increase in power dissipation (approximately multiplied by a factor of 5) and deterioration in delay performance by one order of magnitude. The Hybrid logic stages CSA & PCSA units that are 32.52% and 9.27% faster and achieve optimization in area utilization by 48.68% and 51.09% respectively, at the expense of elevated power dissipation by one order of magnitude. All the circuits were designed and simulated using GPDK 90 nm technology libraries on Cadence Design Suite 6.1.6 platform at 27 °C temperature on 1.2 V supply-rail and SPICE codes were generated as well.