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Engineering Schemes for Bulk FinFET to Simultaneously Improve ESD/Latch-Up Behavior and Hot Carrier Reliability
This article presents a simultaneous impact of selective contact silicidation, silicide, and junction engineering on bulk FinFET's electrostatic discharge (ESD) reliability, latch-up (LU) robustness, and hot carrier-induced (HCI) degradation. The investigations are performed using 3-D TCAD simu...
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Published in: | IEEE transactions on electron devices 2020-07, Vol.67 (7), p.2745-2751 |
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Main Authors: | , , , |
Format: | Article |
Language: | English |
Subjects: | |
Citations: | Items that this one cites Items that cite this one |
Online Access: | Get full text |
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Summary: | This article presents a simultaneous impact of selective contact silicidation, silicide, and junction engineering on bulk FinFET's electrostatic discharge (ESD) reliability, latch-up (LU) robustness, and hot carrier-induced (HCI) degradation. The investigations are performed using 3-D TCAD simulations. To maximize the robustness against HCI reliability and to improve the ESD/LU performance simultaneously, essential technology guidelines are derived based on physical insights developed. With the incorporation of proposed S/D contact silicide and junction engineering, the ESD robustness of FinFETs can be improved by a factor of 6\times compared to conventional approaches. Besides, this is found to improve the overall HCI reliability of bulk FinFETs. Based on these design guidelines, hybrid contact/junction engineered scheme is proposed for the overall robustness of FinFET system-on-chips (SoC). |
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ISSN: | 0018-9383 1557-9646 |
DOI: | 10.1109/TED.2020.2997757 |