Panel-Level Fan-Out RDL-First Packaging for Heterogeneous Integration

In this article, the fan-out chip-last panel-level packaging for heterogeneous integration is investigated. Emphasis is placed on the design, materials, process, fabrication, and simulation of thermomechanical reliability of a heterogeneous integration of one large chip (10 mm \times 10 mm) and tw...

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Bibliographic Details
Published in:IEEE transactions on components, packaging, and manufacturing technology (2011) packaging, and manufacturing technology (2011), 2020-07, Vol.10 (7), p.1125-1137
Main Authors: Lau, John H., Ko, Cheng-Ta, Yang, Kai-Ming, Peng, Chia-Yu, Xia, Tim, Lin, Puru Bruce, Chen, J. J., Huang, Patrick Po-Chun, Liu, Hsing-Ning, Tseng, Tzyy-Jang, Lin, Eagle, Chang, Leo
Format: Article
Language:English
Subjects:
Bonding
Chip formation
Circuit boards
Dielectrics
Fan-out packaging
Fanout
Finite element method
Glass
heterogeneous integration
Packaging
panel-level packaging
Printed circuits
redistribution-layer (RDL)-first or chip last
Reliability analysis
Simulation
Strips
Substrates
Temperature dependence
Thermal cycling
Thermal simulation
Time dependence
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Summary:In this article, the fan-out chip-last panel-level packaging for heterogeneous integration is investigated. Emphasis is placed on the design, materials, process, fabrication, and simulation of thermomechanical reliability of a heterogeneous integration of one large chip (10 mm \times 10 mm) and two small chips (7 mm \times 5 mm) by a fan-out method with a redistribution-layer (RDL)-first substrate fabricated on a 515 mm \times510 mm panel. Reliability assessment by thermomechanical simulation includes thermal cycling of the heterogeneous integration of the three-chip package on a printed circuit board (PCB) assembly that is performed by a nonlinear temperature- and time-dependent finite-element simulation.
ISSN:2156-3950
2156-3985
DOI:10.1109/TCPMT.2020.2996658