Effectiveness of Taguchi and ANOVA in design of differential ring oscillator

In this work, a new circuit of delay cell is proposed to design a wide tuning range differential ring oscillator (DRO). Statistical techniques of Taguchi design of experiments and analysis of variance (ANOVA) are used to optimize the performance parameters of the proposed circuit. Three levels and 3...

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Bibliographic Details
Published in:Analog integrated circuits and signal processing 2020-09, Vol.104 (3), p.331-341
Main Authors: Sharma, Gaurav Kumar, Johar, Arun Kishor, Kumar, Tangudu Bharat, Boolchandani, Dharmendar
Format: Article
Language:English
Subjects:
Circuit design
Circuits and Systems
CMOS
Communications equipment
Design
Design of experiments
Electrical Engineering
Electronic devices
Engineering
Medical equipment
Mixed Signal Letter
MOSFETs
Navigation systems
Optimization
Parameters
Power consumption
Signal,Image and Speech Processing
Statistical methods
Taguchi methods
Tuning
Variance analysis
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Summary:In this work, a new circuit of delay cell is proposed to design a wide tuning range differential ring oscillator (DRO). Statistical techniques of Taguchi design of experiments and analysis of variance (ANOVA) are used to optimize the performance parameters of the proposed circuit. Three levels and 3 factors of width (w1, w3 and w4) for various MOSFETs of delay cell, are considered as major performance controlling factors. Taguchi method identifies the significant level of a factor which affects the specific performance parameter. ANOVA analysis is used to find the critical factor for a specified response. This method is also used to find the optimum values of width w1, w3 and w4 for the overall optimum performance of the proposed circuit. Pre and post layout simulations are carried out in GPDK45 nm CMOS technology to justify the statistical results with the simulated ones. Proposed circuit offers wide tuning range of 88.04% (from 1.67 to 13.96 GHz), phase noise of − 91.38 dBc/Hz (at 10 MHz offset), power consumption of 6.93 mW (at Fosc = 11.34 GHz) and total chip area of 610 μ m 2 . The proposed DRO find its suitability in high speed communication devices, medical equipment’s and navigation systems.
ISSN:0925-1030
1573-1979
DOI:10.1007/s10470-020-01671-4