A SURVEY ON MULTI-OPERAND ADDER

The processors are required to perform computationally intense operations in the modern data world and an Arithmetic Unit (AU) is the heart of the processor that contributes for its performance. It's an ever ending research to optimize the AU w.r.t. architecture area and latency for improving t...

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Bibliographic Details
Published in:Acta Technica Corvininesis 2020-04, Vol.13 (2), p.65-68
Main Authors: Kannappan, S, Mastani, Aruna
Format: Article
Language:English
Subjects:
Adding circuits
Arithmetic and logic units
Convolution
Cost effectiveness
Critical path
Logic
Microprocessors
Multiplication
Optimization
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Summary:The processors are required to perform computationally intense operations in the modern data world and an Arithmetic Unit (AU) is the heart of the processor that contributes for its performance. It's an ever ending research to optimize the AU w.r.t. architecture area and latency for improving the performance of the processor. Adder forms the basic Building block of any AU, and in particular addition of multiple operands is required in complicated arithmetic operations like multiplication, convolution, Transforms etc. Hence existing circuits for efficient Multi-operand adder in terms of circuit area and delay are discussed. The Multi-Operand Adders is optimized in many ways; the most popular methods are discussed in brief with respect to their performance. Memory-based computing is becoming an important approach to achieve fastness and cost effectiveness in contrast to conventional logical approach, and Distributed Arithmetic (DA) is a process of replacing logic elements with small memories or LUTs to optimize the circuit complexity. This paper presents various methods of Multi-Operand Adders and various optimizations for Multi-Operand Addition.
ISSN:2067-3809