Impact of interface trap charges on device level performances of a lateral/vertical gate stacked Ge/Si TFET-on-SELBOX-substrate

This paper reports the TCAD based investigation of the DC/RF and linearity characteristics of a newly proposed dual-material (DM) laterally-stacked (LS) SiO 2 /HfO 2 heterojunction-TFET-on-SELBOX substrate (LS-STFET). Device-level performance comparison is made between the proposed TFET with a dual-...

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Bibliographic Details
Published in:Applied physics. A, Materials science & processing Materials science & processing, 2020-09, Vol.126 (9), Article 681
Main Authors: Singh, Ashish Kumar, Tripathy, Manas Ranjan, Baral, Kamalaksha, Singh, Prince Kumar, Jit, Satyabrata
Format: Article
Language:English
Subjects:
Applied physics
Characterization and Evaluation of Materials
Condensed Matter Physics
Germanium
Hafnium oxide
Heterojunctions
Linearity
Machines
Manufacturing
Materials science
Nanotechnology
Optical and Electronic Materials
Physics
Physics and Astronomy
Processes
Silicon dioxide
Silicon substrates
Surfaces and Interfaces
Thin Films
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Summary:This paper reports the TCAD based investigation of the DC/RF and linearity characteristics of a newly proposed dual-material (DM) laterally-stacked (LS) SiO 2 /HfO 2 heterojunction-TFET-on-SELBOX substrate (LS-STFET). Device-level performance comparison is made between the proposed TFET with a dual-material (DM) vertically-stacked (VS) SiO 2 /HfO 2 heterojunction-TFET-on-SELBOX substrate (VS-STFET). Low bandgap material Ge is used in the source region to form a Ge (source)/Si (channel) heterojunction for enhancing the ON-state current of the presented TFETs. The effects of both donor (+ ve) and acceptor (−ve) type interface trap charges at the channel/SiO 2 region on the DC, analogue/RF and linearity figure of merits have been analyzed for both the devices under study. The LS-STFET is shown to possess higher ON-state current and smaller subthreshold swing (SS) over the VS-STFET. In addition, the LS-STFET is shown to have better DC, analog/RF and linearity performance over VS-STFET in the presence of the donor and acceptor interface trap charges.
ISSN:0947-8396
1432-0630
DOI:10.1007/s00339-020-03869-9