High-Performance Simultaneous Multiprocessing for Heterogeneous System-on-Chip

This paper presents a methodology for simultaneous heterogeneous computing, named ENEAC, where a quad core ARM Cortex-A53 CPU works in tandem with a preprogrammed on-board FPGA accelerator. A heterogeneous scheduler distributes the tasks optimally among all the resources and all compute units run as...

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Bibliographic Details
Published in:arXiv.org 2020-08
Main Authors: Nikov, Kris, Hosseinabady, Mohammad, Asenjo, Rafael, Rodríguezz, Andrés, Navarro, Angeles, Nunez-Yanez, Jose
Format: Article
Language:English
Subjects:
Accelerators
Energy consumption
Field programmable gate arrays
Multiprocessing
Programming languages
System on chip
Task scheduling
Workflow
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Summary:This paper presents a methodology for simultaneous heterogeneous computing, named ENEAC, where a quad core ARM Cortex-A53 CPU works in tandem with a preprogrammed on-board FPGA accelerator. A heterogeneous scheduler distributes the tasks optimally among all the resources and all compute units run asynchronously, which allows for improved performance for irregular workloads. ENEAC achieves up to 17\% performance improvement \ignore{and 14\% energy usage reduction,} when using all platform resources compared to just using the FPGA accelerators and up to 865\% performance increase \ignore{and up to 89\% energy usage decrease} when using just the CPU. The workflow uses existing commercial tools and C/C++ as a single programming language for both accelerator design and CPU programming for improved productivity and ease of verification.
ISSN:2331-8422