Low-Power Area-Efficient Fault Tolerant Adder in Current Mode Multi Valued Logic Using Berger Codes

• Published in: Journal of electronic testing 2020-08, Vol.36 (4), p.555-563
• Main Authors: Mohammadi, Shahram, Omidi, Reza, Lotfinejad, Mohammad
• Format: Article
• Language: English
• Subjects: Adding circuits; CAE) and Design; Checkers; Circuit design; Circuits and Systems; Computer-Aided Engineering (CAD; Delay time; Electrical Engineering; Engineering; Fault detection; Fault tolerance; Multivalued logic
• ISSN: 0923-8174; 1573-0727
• DOI: 10.1007/s10836-020-05887-0

In this paper, we propose a low-power yet area-efficient fault tolerant adder by using Berger codes. The proposed Berger code checker is designed by using the current mode multi-valued logic (CM-MVL) circuits. The proposed structure, which is more area and power efficient than state-of-the-art fault tolerant adders, is able to detect all single and multi-bit unidirectional faults. The efficiency of the proposed fault tolerant adder is evaluated by comparing its characteristics to those of two state-of-the-art fault detection schemes in adders as well as the conventional duplex and parity bit checkers in a 90 nm technology. The results reveal that the proposed 64-bit Berger code checker for adders imposes up to 6.7% and 27.2% delay and area penalties, respectively with a cost of static power dissipation. In the proposed scheme, in sub threshold regime, the power penalty is just 1%, while its area overhead is only 31%. The drawback of using this scheme in sub threshold regime is that delay time introduced to the circuit is unacceptable. So, depending on the application, we should choose one of the above-mentioned schemes.