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On the impact of the synchronization constraint and interconnections in quantum-dot cellular automata

Quantum-dot Cellular Automata (QCA) is an emerging nanotechnology with remarkable performance and energy efficiency. Computation and information transfer in QCA are based on field forces rather than electric currents. As a consequence, new strategies are required for design automation approaches in...

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Published in:Microprocessors and microsystems 2020-07, Vol.76, p.103109, Article 103109
Main Authors: Sill Torres, Frank, Silva, Pedro A., Fontes, Geraldo, Walter, Marcel, Nacif, José Augusto M., Ferreira, Ricardo Santos, Vilela Neto, Omar Paranaiba, Chaves, Jeferson F., Wille, Robert, Niemann, Philipp, Große, Daniel, Drechsler, Rolf
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Language:English
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Summary:Quantum-dot Cellular Automata (QCA) is an emerging nanotechnology with remarkable performance and energy efficiency. Computation and information transfer in QCA are based on field forces rather than electric currents. As a consequence, new strategies are required for design automation approaches in order to cope with the arising challenges. One of these challenges is the transport of information, which is affected by two particularities of the QCA technology. First, information flow in QCA is controlled by external clocks, and second, QCA is a planar technology in which gates, as well as interconnections, are mostly located in the same layer. The former demands proper synchronization already during the circuit design phase, while the latter results in high area costs for interconnections. This work focuses on both constraints and discusses its impact on the implementation of QCA circuits. Further, the concept of local and global synchronicity in QCA circuits is explored. The obtained results indicate that relaxing the global synchronicity constraint can reduce design size by about 70% while the throughput performance declines by similar values. Additionally, it can be shown that the impact of interconnections in QCA, like wires, fan-outs, and crossovers, is indeed substantial. That means, up to 75% of the total area is occupied by interconnections.
ISSN:0141-9331
1872-9436
DOI:10.1016/j.micpro.2020.103109