A 4-GHz Sub-Harmonically Injection-Locked Phase-Locked Loop With Self-Calibrated Injection Timing and Pulsewidth

A 4-GHz sub-harmonically injection-locked phase-locked loop (ILPLL) with on-chip calibration is presented. The injection timing and pulsewidth of the injected pulse are self-calibrated to achieve low phase noise. The phase noise of the proposed ILPLL was −112.3 dBc/Hz at 1-MHz offset frequency, wher...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2020-10, Vol.55 (10), p.2724-2733
Main Authors: Jin, Xuefan, Park, Woosung, Kang, Dong-Seok, Ko, Youngjun, Kwon, Kee-Won, Chun, Jung-Hoon
Format: Article
Language:English
Subjects:
Calibration
Clocks
CMOS
Injection-locked phase-locked loop (ILPLL)
injection-locked ring oscillator (ILRO)
Jitter
Phase locked loops
Phase locked systems
phase-locked loop (PLL)
Power consumption
ring oscillator
Ring oscillators
self-calibrated injection pulsewidth
self-calibrated injection timing
Switches
Timing
Vibration
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Description
Summary:A 4-GHz sub-harmonically injection-locked phase-locked loop (ILPLL) with on-chip calibration is presented. The injection timing and pulsewidth of the injected pulse are self-calibrated to achieve low phase noise. The phase noise of the proposed ILPLL was −112.3 dBc/Hz at 1-MHz offset frequency, whereas that of the conventional PLL was −104.8 dBc/Hz. The measured integrated jitter from 10 kHz to 30 MHz was 710 fs, and the corresponding reference spur level was −61.6 dBc with the proposed calibration technique. Fabricated in a 28-nm CMOS process, the proposed ILPLL occupies 0.09 mm 2 . Operating at 4 GHz, it consumes 11.4 mW from a 1.0-V power supply.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2020.3005806