Design Methodology for Distributed Large-Scale ERSFQ Bias Networks

Rapid single-flux quantum (RSFQ) circuits have recently attracted considerable attention as a promising cryogenic beyond CMOS technology for exascale computing. Energy-efficient RSFQ (ERSFQ) is an energy-efficient, inductive bias scheme for RSFQ circuits, where the power dissipation is drastically l...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2020-11, Vol.28 (11), p.2438-2447
Main Authors: Krylov, Gleb, Friedman, Eby G.
Format: Article
Language:English
Subjects:
Bias
Circuit design
Circuits
Clocks
CMOS
Design parameters
Guidelines
Inductance
Inductors
Josephson junctions
Logic gates
Parasitics (electronics)
Power dissipation
Resistors
Single-flux quantum (SFQ)
superconductive digital electronics
superconductive integrated circuits
Superconductivity
Topology
Transmission lines
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Summary:Rapid single-flux quantum (RSFQ) circuits have recently attracted considerable attention as a promising cryogenic beyond CMOS technology for exascale computing. Energy-efficient RSFQ (ERSFQ) is an energy-efficient, inductive bias scheme for RSFQ circuits, where the power dissipation is drastically lowered by eliminating the bias resistors, while the cell library remains unchanged. An ERSFQ bias scheme requires the introduction of multiple circuit elements-current limiting Josephson junctions, bias inductors, and feeding Josephson transmission lines (FJTLs). In this article, parameter guidelines and design techniques for ERSFQ circuits are presented. The proposed guidelines enable more robust circuits resistant to severe variations in supplied bias currents. Trends are considered, and advantageous tradeoffs are discussed for the different components within a bias network. The guidelines provide a means to decrease the size of an FJTL and, thereby, reduce the physical area, power dissipation, and overall bias currents, supporting further increases in circuit complexity. A distributed approach to ERSFQ FJTL is also presented to simplify placement and minimize the effects of the parasitic inductance of the bias lines. This methodology and related circuit techniques are applicable to automating the synthesis of bias networks to enable large-scale ERSFQ circuits.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2020.3023054