Tri-State Nanoelectromechanical Memory Switches for the Implementation of a High-Impedance State

Tri-state nanoelectromechanical (NEM) memory switches are proposed for the implementation of high-impedance state 0 in addition to low-impedance states 1 and 2 for the improvement of conventional complementary metal-oxide-semiconductor-NEM (CMOS-NEM) reconfigurable logic (RL) operations. Although it...

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Bibliographic Details
Published in:IEEE access 2020, Vol.8, p.202006-202012
Main Authors: Baek, Gwangryeol, Yoon, Jisoo, Choi, Woo Young
Format: Article
Language:English
Subjects:
CMOS
Design methodology
Design modifications
High impedance
Impedance
Metal oxides
nanoelectromechanical (NEM) memory switch
Nanoelectromechanical systems
Reconfigurable logic
reconfigurable logic (RL)
RL circuits
Routing
Switches
Throughput
tri-state operation
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Summary:Tri-state nanoelectromechanical (NEM) memory switches are proposed for the implementation of high-impedance state 0 in addition to low-impedance states 1 and 2 for the improvement of conventional complementary metal-oxide-semiconductor-NEM (CMOS-NEM) reconfigurable logic (RL) operations. Although it is well known that the high impedance state of routing switches is essential to prevent the unnecessary data throughput of RL circuits, previously proposed NEM memory switches have only implemented binary states: states 1 and 2. On the contrary, our proposed NEM memory switches can have tri-states, which are achieved by modifying their operation methods and design guidelines.
ISSN:2169-3536
2169-3536
DOI:10.1109/ACCESS.2020.3036189