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Tri-State Nanoelectromechanical Memory Switches for the Implementation of a High-Impedance State
Tri-state nanoelectromechanical (NEM) memory switches are proposed for the implementation of high-impedance state 0 in addition to low-impedance states 1 and 2 for the improvement of conventional complementary metal-oxide-semiconductor-NEM (CMOS-NEM) reconfigurable logic (RL) operations. Although it...
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Published in: | IEEE access 2020, Vol.8, p.202006-202012 |
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creator | Baek, Gwangryeol Yoon, Jisoo Choi, Woo Young |
description | Tri-state nanoelectromechanical (NEM) memory switches are proposed for the implementation of high-impedance state 0 in addition to low-impedance states 1 and 2 for the improvement of conventional complementary metal-oxide-semiconductor-NEM (CMOS-NEM) reconfigurable logic (RL) operations. Although it is well known that the high impedance state of routing switches is essential to prevent the unnecessary data throughput of RL circuits, previously proposed NEM memory switches have only implemented binary states: states 1 and 2. On the contrary, our proposed NEM memory switches can have tri-states, which are achieved by modifying their operation methods and design guidelines. |
doi_str_mv | 10.1109/ACCESS.2020.3036189 |
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Although it is well known that the high impedance state of routing switches is essential to prevent the unnecessary data throughput of RL circuits, previously proposed NEM memory switches have only implemented binary states: states 1 and 2. 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Although it is well known that the high impedance state of routing switches is essential to prevent the unnecessary data throughput of RL circuits, previously proposed NEM memory switches have only implemented binary states: states 1 and 2. On the contrary, our proposed NEM memory switches can have tri-states, which are achieved by modifying their operation methods and design guidelines.</description><subject>CMOS</subject><subject>Design methodology</subject><subject>Design modifications</subject><subject>High impedance</subject><subject>Impedance</subject><subject>Metal oxides</subject><subject>nanoelectromechanical (NEM) memory switch</subject><subject>Nanoelectromechanical systems</subject><subject>Reconfigurable logic</subject><subject>reconfigurable logic (RL)</subject><subject>RL circuits</subject><subject>Routing</subject><subject>Switches</subject><subject>Throughput</subject><subject>tri-state operation</subject><issn>2169-3536</issn><issn>2169-3536</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2020</creationdate><recordtype>article</recordtype><sourceid>ESBDL</sourceid><sourceid>DOA</sourceid><recordid>eNpNUdtKxDAQLaKgqF_gS8DnrrlfHmXxsuDlYfU5psnUzdI2a1oR_95oRRwGZjgz58zAqaozgheEYHNxuVxerdcLiileMMwk0WavOqJEmpoJJvf_9YfV6ThucQldIKGOqpenHOv15CZAD25I0IGfcurBb9wQvevQPfQpf6L1R5z8BkbUpoymDaBVv-ugh6FQYxpQapFDt_F1U5cBBDd4QD-yJ9VB67oRTn_rcfV8ffW0vK3vHm9Wy8u72nOspzq0ilNvFIhGNYHJwDEmRFEvAxO4Ea00RnDZBM4kdUaKwFstDRfGN5z7hh1Xq1k3JLe1uxx7lz9tctH-ACm_Wpen6DuwEAxumKau8YJTFbQSTmivlBbKBEyK1vmstcvp7R3GyW7Tex7K-5ZyibXQVOGyxeYtn9M4Zmj_rhJsv52xszP22xn760xhnc2sCAB_DEN5Sc6-AJP-iNU</recordid><startdate>2020</startdate><enddate>2020</enddate><creator>Baek, Gwangryeol</creator><creator>Yoon, Jisoo</creator><creator>Choi, Woo Young</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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source | IEEE Xplore Open Access Journals |
subjects | CMOS Design methodology Design modifications High impedance Impedance Metal oxides nanoelectromechanical (NEM) memory switch Nanoelectromechanical systems Reconfigurable logic reconfigurable logic (RL) RL circuits Routing Switches Throughput tri-state operation |
title | Tri-State Nanoelectromechanical Memory Switches for the Implementation of a High-Impedance State |
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