A 12-b 18-GS/s RF Sampling ADC With an Integrated Wideband Track-and-Hold Amplifier and Background Calibration

• Published in: IEEE journal of solid-state circuits 2020-12, Vol.55 (12), p.3210-3224
• Main Authors: Ali, Ahmed M. A., Dinc, Huseyin, Bhoraskar, Paritosh, Bardsley, Scott, Dillon, Chris, McShea, Matthew, Periathambi, Joel Prabhakar, Puckett, Scott
• Format: Article
• Language: English
• Subjects: Algorithms; Amplifiers; Analog to digital conversion; Analog to digital converters; Analog-to-digital converter (ADC); background calibration; Bandwidth; Bandwidths; Broadband; Calibration; Clocks; Cutting; DAC calibration; digital assistance; Harmonic distortion; interleaved; Linearity; non-linear calibration; Nonlinearity; pipeline; Pipelines; Power demand; Pseudorandom; Radio frequency; Randomization; reference calibration; RF sampling; sample-and-hold; sample-and-hold amplifier (SHA); Sampling; Switches; track-and-hold; track-and-hold amplifier (THA)
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2020.3023882

We discuss a 12-b 18-GS/s analog-to-digital converter (ADC) implemented in 16-nm FinFET process. The ADC is composed of an integrated high-speed track-and-hold amplifier (THA) driving up to eight interleaved pipeline ADCs that employ open-loop inter-stage amplifiers. Up to 10 GS/s, the THA operates at the full sampling rate using a non-interleaved single sample network, thereby eliminating the interleaving sampling time and bandwidth mismatch. Above 10 GS/s, the THA is programmed to use two ping-ponged, or an optional (2 + 1) randomized, sample networks to spread the residual post-calibration interleaving spurs in the noise floor. The THA enables an input bandwidth of 18 GHz and employs dither injection and optional pseudorandom chopping. In the pipeline stages, dither-based background calibration detects and corrects gain, settling, memory, and kick-back errors. New dither-based background calibration algorithms are employed to detect and correct the arbitrary non-linearity in the form of integral non-linearity (INL) breaks and harmonic distortion up to the fifth order in the THA and in the references, DACs, and inter-stage open-loop amplifiers of the pipeline ADCs. Moreover, new dither-based background calibration is implemented to detect and correct the chopping non-idealities, memory errors, interleaving mismatches, and order-dependent randomization errors. Compared to the fastest state-of-the-art with similar performance, this ADC achieves 80% higher sample rate and 2.4 \times higher input bandwidth, and incorporates a THA that supports a 3.3 \times higher non-interleaved sample rate.