High‐reliability gate driver circuit to prevent ripple voltage

• Published in: Journal of the Society for Information Display 2021-01, Vol.29 (1), p.68-77
• Main Authors: Lee, Jungwoo, Oh, Jongsu, Jung, Eun Kyo, Park, KeeChan, Jeon, Jae‐Hong, Lee, Soo‐Yeon, Kim, Yong‐Sang
• Format: Article
• Language: English
• Subjects: a‐IGZO TFT; Circuit reliability; Circuits; Driver circuits; duty ratio; gate driver circuit; Gates (circuits); Power consumption; reliability; ripple voltage; Ripples; Stability; Threshold voltage; Transistors
• ISSN: 1071-0922; 1938-3657
• DOI: 10.1002/jsid.969

In this paper, a high‐reliability gate driver circuit is proposed to prevent multiple outputs. The proposed circuit ensures reliability of the pull‐up thin‐film transistor (TFT) by periodically discharging the Q node voltage to the low‐level voltage (VGL) in the off stage. In addition, the output node is composed of two pull‐down TFTs that are driven alternately to ensure stability against bias stress. Thus, because the reliabilities of the pull‐up and pull‐down TFTs can be guaranteed simultaneously, the stability of the entire circuit is improved. Based on the simulation results, the rising and falling times of the output pulse are stable within 1.77 and 1.28 μs, respectively, even when the threshold voltage of the entire TFT is shifted by +10.0 V. In addition, the ripple voltage of the proposed circuit is almost eliminated and is within 0.79% of the total swing voltage. Moreover, through current is prevented in the proposed circuit because the turn‐on durations of the pull‐up and pull‐down units are completely nonoverlapping, which suggests that unnecessary power consumption can be eliminated. Therefore, based on 2,160 stages, the total power consumption of the proposed circuit is reduced by 34.7 mW from 276.3 to 241.6 mW. We propose a new gate driver circuit that can prevent output ripple voltage through stably driving of pull‐down TFTs. In the ripple voltage generation period, the pull‐down TFT operates in the saturation region of the I–V curve without any current path. Also, the output node is composed of two pull‐down TFTs are driven alternately to ensure stability against bias stress.