Experimental Implementation of Fault Tolerance Using Dynamic Partial Reconfiguration on Xilinx Zynq-7000 SoC

• Published in: Denki Gakkai ronbunshi. D, Sangyō ōyō bumonshi 2021/02/01, Vol.141(2), pp.93-99
• Main Authors: Ogido, Seiya, Ichikawa, Shuichi, Fujieda, Naoki, Yamada, Chikatoshi, Miyagi, Kei
• Format: Article
• Language: Japanese
• Subjects: Data transfer (computers); Dynamic Partial Reconfiguration (DPR); embedded Linux; embedded systems; Fault tolerance; Field programmable gate arrays; FPGA; Microprocessors; Reconfiguration; Redundancy
• ISSN: 0913-6339; 2187-1094; 1348-8163; 2187-1108
• DOI: 10.1541/ieejias.141.93

In our previous paper, the authors proposed a fault tolerant system that adopts field programmable gate arrays (FPGA) with dynamic partial reconfiguration (DPR), based on autonomous control of reconfiguration. This study presents an experimental implementation of the proposed system that utilizes the DPR feature of Xilinx Zynq-7000 SoC. The control logic of DPR is implemented as a Linux software on the embedded ARM processor of Zynq-7000. DPR is invoked via PCAP, which is the dedicated interface for the embedded ARM processor. Four tiles (reconfigurable areas) are prepared and dynamically reconfigured to avoid the firm error of SRAM-type FPGAs. An experimental fault-tolerant system with triple redundancy and logic roving is implemented, and the measurement results of the reconfiguration time and data transfer time are presented.