Two-Dimensional Mapping of Interface Thermal Resistance by Transient Thermal Measurement

• Published in: IEEE transactions on industrial electronics (1982) 2021-05, Vol.68 (5), p.4448-4456
• Main Authors: Gao, Shan, Ngo, Khai D. T., Lu, Guo-Quan
• Format: Article
• Language: English
• Subjects: Copper; Defects; Heat transfer; Heating systems; Insulated gate bipolar transistors; Interfaces; Mapping; Measurement techniques; Movable thermal probe; Multilayers; Nondestructive testing; Parameter sensitivity; Power converters; Probes; Reliability; Semiconductor devices; structure function; Substrates; Temperature measurement; Thermal analysis; Thermal cycling; Thermal measurement; Thermal resistance; transient thermal measurement; two-dimensional (2-D) mapping
• ISSN: 0278-0046; 1557-9948
• DOI: 10.1109/TIE.2020.2984997

Bonded interfaces in power converters add thermal resistances to heat dissipation. Under cyclic power, temperature, or chemical loading, these interfaces degrade, raising the thermal resistances. Reliability of the thermal interfaces is especially problematic when the bonded area is large because the larger the area the more likely it is to have preexisting defects from processing. To help qualifying the development of a bonding process and quantifying the interface reliability, it would be desirable to have a simple, reliable, and nondestructive measurement technique to obtain a 2-D map of the interface thermal resistance across a large bonded area. Based on the transient thermal method of JEDEC standard 51-14, in this article, we develop a measurement technique that involves moving a thermal probe discretely across a large-area bonded substrate and acquiring the thermal interface resistance under the probe at each location. The probe is made by custom-packaging an insulated-gate bipolar transistor (IGBT) power device. An analytical thermal model is developed to gain insights into the effects of probe materials and structural parameters on the sensitivity of the measurement technique. To obtain a 2-D thermal resistance map of a bonded substrate, the probe is thermally coupled to the substrate at one location through a thermal pad or grease; the device is powered up to a steady-state junction temperature; the power is cutoff; and then the junction temperature during cool-down is recorded. The recorded temperature data are analyzed to derive a thermal structure function of the multilayer material stack. The process is repeated at other locations until a 2-D map of the interface thermal resistance across the entire substrate is completed. This technique is demonstrated on copper-copper bonded samples using either a thermal grease or sintered silver. The resolution of the 2-D mapping technique is evaluated by a copper-grease-copper stack with defects implanted at the bond line.