40 nm 1T-1MTJ 128 Mb STT-MRAM With Novel Averaged Reference Voltage Generator Based on Detailed Analysis of Scaled-Down Memory Cell Array Design

The development of STT-MRAM technology is currently in progress and has been successively disclosed by major LSI vendors recently. In order to advance STT-MRAM technology and expand its areas of application, challenges relative to further device scaling need to be addressed. In this study, an increa...

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Bibliographic Details
Published in:IEEE transactions on magnetics 2021-03, Vol.57 (3), p.1-9
Main Authors: Koike, Hiroki, Tanigawa, Takaho, Watanabe, Toshinari, Nasuno, Takashi, Noguchi, Yasuo, Yasuhira, Mitsuo, Yoshiduka, Toru, Ma, Yitao, Honjo, Hiroaki, Nishioka, Koichi, Miura, Sadahiko, Inoue, Hirofumi, Ikeda, Shoji, Endoh, Tetsuo
Format: Article
Language:English
Subjects:
Access time
Array design
Arrays
Circuit design
CMOS
Computer architecture
Electrical resistance measurement
Generators
Magnetism
Microprocessors
Monte Carlo simulation
reference generator
Resistance
STT-MRAM
Time measurement
Transistors
variation tolerant
Voltage generators
Voltage measurement
Wiring
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Summary:The development of STT-MRAM technology is currently in progress and has been successively disclosed by major LSI vendors recently. In order to advance STT-MRAM technology and expand its areas of application, challenges relative to further device scaling need to be addressed. In this study, an increased wiring resistance in a deep sub-100 nm process by which the read operation yield is degraded was analyzed. The yield degradation was quantified by analyzing the conventional cell array using Monte-Carlo SPICE simulations. A new circuit was proposed to decrease the fail bit rate by an averaged reference voltage ( V_{\mathrm {ref}} ) generator. The simulated results indicated that the new V_{\mathrm {ref}} generator improved the fail bit rate by 1 order of magnitude compared to the conventional array. To demonstrate the circuit operation, a 128 Mb STT-MRAM chip was designed and fabricated using 40 nm CMOS and 37 nm MTJ technologies. For the first time, the chip measurements successfully demonstrated the operation of the proposed device-variation tolerant array architecture with the averaged V_{\mathrm {ref}} generator, presenting a 30 ns read access time.
ISSN:0018-9464
1941-0069
DOI:10.1109/TMAG.2020.3038110