Experimental Body-input Three-stage DC offset Calibration Scheme for Memristive Crossbar

Reading several ReRAMs simultaneously in a neuromorphic circuit increases power consumption and limits scalability. Applying small inference read pulses is a vain attempt when offset voltages of the read-out circuit are decisively more. This paper presents an experimental validation of a three-stage...

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Bibliographic Details
Published in:arXiv.org 2021-03
Main Authors: Mohan, Charanraj, Camuñas-Mesa, L A, Vianello, Elisa, Reita, Carlo, José M de la Rosa, Serrano-Gotarredona, Teresa, Linares-Barranco, Bernabé
Format: Article
Language:English
Subjects:
Calibration
Circuit boards
Circuit design
CMOS
Electrical noise
Memristors
MOSFETs
Power consumption
Printed circuits
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Summary:Reading several ReRAMs simultaneously in a neuromorphic circuit increases power consumption and limits scalability. Applying small inference read pulses is a vain attempt when offset voltages of the read-out circuit are decisively more. This paper presents an experimental validation of a three-stage calibration scheme to calibrate the DC offset voltage across the rows of the memristive crossbar. The proposed method is based on biasing the body terminal of one of the differential pair MOSFETs of the buffer through a series of cascaded resistor banks arranged in three stages: coarse, fine and finer stages. The circuit is designed in a 130 nm CMOS technology, where the OxRAM-based binary memristors are built on top of it. A dedicated PCB and other auxiliary boards have been designed for testing the chip. Experimental results validate the presented approach, which is only limited by mismatch and electrical noise.
ISSN:2331-8422
DOI:10.48550/arxiv.2103.02651