Selection Methodology for Si Power MOSFETs Used to Enhance SiC Power MOSFET Short-Circuit Capability With the BaSIC(EMM) Topology

• Published in: IEEE transactions on power electronics 2021-07, Vol.36 (7), p.8243-8252
• Main Authors: Kanale, Ajit, Baliga, B. Jayant
• Format: Article
• Language: English
• Subjects: BaSIC; Bias; EMM; Inverters; Logic gates; MOSFET; MOSFETs; power MOSFETs; Resistance; short circuit capability; Short circuits; Silicon; Silicon carbide; Topology; Tradeoffs
• ISSN: 0885-8993; 1941-0107
• DOI: 10.1109/TPEL.2020.3043281

The BaSIC(EMM) topology has been previously demonstrated to improve the short-circuit (SC) capability of 1.2-kV SiC power MOSFET s from 3.5 to 7.4 μs while producing a 17% increase in the net on -state resistance. However, a SC time of 10 μs could not be achieved. In this article, a systematic procedure for selection of the Si power MOSFET used in the BaSIC(EMM) topology is described based on information published by manufacturers of Si power MOSFET s in their datasheets. A tradeoff curve between the Si EMM drain saturation current at 150 °C versus its on -resistance at 25 °C is proposed in this article for determination of the best Si EMM product. The proposed methodology allowed identification of a superior Si EMM device. It was experimentally validated that a SC with-stand time of 11 μs, under a gate bias of 20 V applied to the 1.2-kV SiC power MOSFET at a drain bias of 800 V, was achievable with an increase in on -resistance of only 3.6%. These experimental results demonstrate a greatly improved tradeoff curve between SC time and increase in on -resistance.