Demonstration of CMOS-Compatible Multi-Level Graphene Interconnects With Metal Vias

Doped-multilayer-graphene (DMLG) interconnects employing the subtractive-etching (SE) process have opened a new pathway for designing interconnects at advanced technology nodes, where conventional metal wires suffer from significant resistance increase, self-heating (SH), electromigration (EM), and...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2021-04, Vol.68 (4), p.2083-2091
Main Authors: Agashiwala, Kunjesh, Jiang, Junkai, Parto, Kamyar, Zhang, Dujiao, Yeh, Chao-Hui, Banerjee, Kaustav
Format: Article
Language:English
Subjects:
CMOS
CMOS-compatible
Copper
doped multilayer graphene (DMLG)
dual-damascene (DD)
Electromigration
electromigration (EM)
Graphene
graphene capping-layer
Integrated circuit interconnections
Interconnections
interconnects
Metals
multi-level
Multilayers
Nodes
reliability
Reliability aspects
Resistance
self-heating (SH)
Silicon compounds
Silicon dioxide
Solid phases
solid-phase diffusion
Substrates
subtractive etching
Wires
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Summary:Doped-multilayer-graphene (DMLG) interconnects employing the subtractive-etching (SE) process have opened a new pathway for designing interconnects at advanced technology nodes, where conventional metal wires suffer from significant resistance increase, self-heating (SH), electromigration (EM), and various integration challenges. Even though single-level scaled graphene wires have been shown to possess better performance and reliability with respect to dual-damascene (DD) and SE-enabled metal wires, a multi-level graphene interconnect technology (with vias ) has remained elusive, which is of paramount importance for its integration in future technology nodes. This work, for the first time, addresses that need by engineering a CMOS-compatible solid-phase growth technique to yield large-area multilayer graphene (MLG) on dielectric (SiO 2 ) and metal (Cu) substrates and subsequently demonstrating multi-level MLG interconnects with metal vias . Using rigorous theoretical and experimental analyses, we demonstrate that multi-level MLG interconnects with metal vias undergo < 2% change in the via resistance under accelerated stress conditions, demonstrating its superior reliability against SH and EM, making them ideal candidates for sub-10 nm nodes.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2021.3061637