An Ultra-Low-Power Image Signal Processor for Hierarchical Image Recognition With Deep Neural Networks

We propose an ultra-low-power (ULP) image signal processor (ISP) that performs on-the-fly in-processing frame compression/decompression and hierarchical event recognition to exploit the temporal and spatial sparsity in an image sequence. This approach reduces energy consumption spent processing and...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2021-04, Vol.56 (4), p.1071-1081
Main Authors: An, Hyochan, Schiferl, Sam, Venkatesan, Siddharth, Wesley, Tim, Zhang, Qirui, Wang, Jingcheng, Choo, Kyojin D., Liu, Shiyu, Liu, Bowen, Li, Ziyun, Gong, Luyao, Zhong, Hengfei, Blaauw, David, Dreslinski, Ronald, Kim, Hun Seok, Sylvester, Dennis
Format: Article
Language:English
Subjects:
Artificial neural networks
CMOS
Deep neural network (DNN)
Energy consumption
energy-efficient processor
Engines
event recognition
Face recognition
Image coding
Image compression
image signal processor (ISP)
Image transmission
Imaging
Microprocessors
Neural networks
Object recognition
Power management
Random access memory
Signal processing
Streaming media
Transform coding
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Summary:We propose an ultra-low-power (ULP) image signal processor (ISP) that performs on-the-fly in-processing frame compression/decompression and hierarchical event recognition to exploit the temporal and spatial sparsity in an image sequence. This approach reduces energy consumption spent processing and transmitting unimportant image data to achieve a 16 \times imaging system energy gain in an intruder detection scenario. The ISP was fabricated in 40-nm CMOS and consumes only 170 \mu \text{W} at 5 frames/s for neural network-based intruder detection and 192 \times compressed image recording.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2020.3041858