A Single-Trim Switched Capacitor CMOS Bandgap Reference With a 3σ Inaccuracy of +0.02%, −0.12% for Battery-Monitoring Applications

This article presents a single-trim switched capacitor (SC) CMOS bandgap reference (BGR) for battery monitoring applications. For a single-temperature trimming, \beta -compensation and curvature correction techniques are employed to minimize non-proportional-to-absolute-temperature (PTAT) errors. I...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2021-04, Vol.56 (4), p.1197-1206
Main Authors: Boo, Jun-Ho, Cho, Kang-Il, Kim, Ho-Jin, Lim, Jae-Geun, Kwak, Yong-Sik, Lee, Seung-Hoon, Ahn, Gil-Cho
Format: Article
Language:English
Subjects:
Amplification
Analog to digital conversion
Analog to digital converters
Bandgap reference (BGR)
Batteries
Capacitors
Circuits
CMOS
curvature correction
delta-sigma analog-to-digital converter (ADC)
Energy gap
Low pass filters
mismatch averaging
Monitoring
Photonic band gap
Room temperature
Semiconductor devices
single room-temperature trimming
Temperature dependence
Temperature measurement
Transistors
Trimming
Voltage measurement
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Summary:This article presents a single-trim switched capacitor (SC) CMOS bandgap reference (BGR) for battery monitoring applications. For a single-temperature trimming, \beta -compensation and curvature correction techniques are employed to minimize non-proportional-to-absolute-temperature (PTAT) errors. In conjunction with these techniques, this article proposes dynamic element matching (DEM) techniques with low-pass filtering which employs the decimation filter of a delta-sigma analog-to-digital converter (ADC) in a digital domain. It achieves a further reduction of non-PTAT errors resulting from mismatches of the bias current, of the PNP transistor current gain ( \beta ), and of the gain coefficient in the SC summing amplifier. The remaining PTAT errors are canceled out using a single room-temperature trimming. The bandgap circuit is implemented using vertical PNP transistors with a \beta of about 2.7 at 27 °C in a 0.18- \mu \text{m} CMOS process. The proposed SC BGR achieves a 3\sigma inaccuracy of +0.02%, −0.12% from −40 °C to 125 °C. From a 1.8-V supply voltage, it consumes 17~\mu \text{A} at 27 °C and occupies an active area of 0.38 mm 2 .
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2020.3044165